SiON gradient concept
Embodiments of the present disclosure generally relate to methods and devices for use of low temperature polysilicon (LTPS) thin film transistors in liquid crystal display (LCD) and organic light-emitting diode (OLED) displays.
1. A thin film transistor, comprising:
a substrate;
two dual layers disposed over the substrate, each dual layer comprising:
a first inorganic layer having a first refractive index;
a second inorganic layer having a second refractive index, the first refractive index being less than the second refractive index; and
a transition stack disposed between the first inorganic layer and the second inorganic layer, the transition stack comprising at least a third inorganic layer and a fourth inorganic layer, wherein:
the third inorganic layer is disposed on the first inorganic layer and has a third refractive index;
the fourth inorganic layer is disposed on the third inorganic layer and has a fourth refractive index;
the third refractive index is greater than the first refractive index and less than the fourth refractive index; and
the fourth refractive index is greater than the third refractive index and less than the second refractive index.
2. The thin film transistor of claim 1 , wherein the first inorganic layer comprises silicon oxide and the second inorganic layer comprises silicon nitride and is disposed on the fourth inorganic layer.
3. The thin film transistor of claim 1 , further comprising:
a layer of indium tin oxide disposed over the two dual layers.
4. The thin film transistor of claim 3 , further comprising:
a polymer layer disposed over the two dual layers and under the indium tin oxide layer.
5. The thin film transistor of claim 1 , further comprising:
a blocking layer disposed over the substrate and under the two dual layers, the blocking layer comprising:
a fifth inorganic layer having a fifth refractive index;
a sixth inorganic layer having a sixth refractive index, the fifth refractive index being greater than the sixth refractive index; and
a transition stack disposed between the fifth inorganic layer and the sixth inorganic layer, the transition stack comprising at least a seventh inorganic layer and an eighth inorganic layer, wherein:
the seventh inorganic layer is disposed on the fifth inorganic layer and has a seventh refractive index;
the eighth inorganic layer is disposed on the seventh inorganic layer and has an eighth refractive index;
the seventh refractive index is less than the fifth refractive index and greater than the eighth refractive index; and
the eighth refractive index is less than the seventh refractive index and greater than the sixth refractive index.
6. The thin film transistor of claim 5 , wherein the fifth inorganic layer comprises silicon nitride and the sixth inorganic layer comprises silicon oxide.
7. The thin film transistor of claim 6 , wherein:
the first inorganic layer comprises silicon nitride; and
the second inorganic layer comprises silicon oxide.
8. The thin film transistor of claim 5 , further comprising:
a layer of indium tin oxide disposed over the two dual layers.
9. The thin film transistor of claim 8 , further comprising:
a polymer layer disposed over the two dual layers and under the indium tin oxide layer.
10. The thin film transistor of claim 9 , further comprising:
a polyimide layer disposed over the indium tin oxide layer.
11. A thin film transistor, comprising:
a glass substrate;
a gate insulator dual layer disposed over the glass substrate, the gate insulator dual layer comprising:
a first inorganic layer having a first refractive index;
a second inorganic layer having a second refractive index, the first refractive index being less than the second refractive index; and
a transition stack disposed between the first inorganic layer and the second inorganic layer, the transition stack comprising at least a third inorganic layer and a fourth inorganic layer, wherein:
the third inorganic layer is disposed on the first inorganic layer and has a third refractive index;
the fourth inorganic layer is disposed on the third inorganic layer and has a fourth refractive index;
the third refractive index is greater than the first refractive index and less than the fourth refractive index; and
the fourth refractive index is greater than the third refractive index and less than the second refractive index;
an interlayer dielectric layer disposed over the gate insulator dual layer, the interlayer dielectric layer comprising:
a fifth inorganic layer having a fifth refractive index;
a sixth inorganic layer having a sixth refractive index, the fifth refractive index being less than the sixth refractive index; and
a transition stack disposed between the fifth inorganic layer and the sixth inorganic layer, the transition stack comprising at least a seventh inorganic layer and an eighth inorganic layer, wherein:
the seventh inorganic layer is disposed on the fifth inorganic layer and has a seventh refractive index;
the eighth inorganic layer is disposed on the seventh inorganic layer and has an eighth refractive index;
the seventh refractive index is greater than the fifth refractive index and less than the eighth refractive index; and
the eighth refractive index is greater than the seventh refractive index and less than the sixth refractive index.
12. The thin film transistor of claim 11 , wherein:
the first inorganic layer comprises silicon oxide;
the second inorganic layer comprises silicon nitride;
the fifth inorganic layer comprises silicon oxide; and
the sixth inorganic layer comprises silicon nitride.
13. The thin film transistor of claim 12 , further comprising:
a layer of indium tin oxide disposed over the interlayer dielectric layer.
14. The thin film transistor of claim 13 , further comprising:
a polymer layer between the indium tin oxide layer and the interlayer dielectric layer.
15. The thin film transistor of claim 11 , further comprising:
a blocking layer disposed between the substrate and the gate insulator dual layer, the blocking layer comprising:
a ninth inorganic layer having a ninth refractive index;
a tenth inorganic layer having a tenth refractive index, the ninth refractive index being greater than the tenth refractive index; and
a transition stack disposed between the ninth inorganic layer and the tenth inorganic layer, the transition stack comprising at least an eleventh inorganic layer and a twelfth inorganic layer, wherein:
the eleventh inorganic layer is disposed on the ninth inorganic layer and has an eleventh refractive index;
the twelfth inorganic layer is disposed on the eleventh inorganic layer and has a twelfth refractive index;
the eleventh refractive index is less than the ninth refractive index and greater than the twelfth refractive index; and
the twelfth refractive index is less than the eleventh refractive index and greater than the tenth refractive index.
16. The thin film transistor of claim 15 , wherein:
the first inorganic layer comprises silicon oxide;
the second inorganic layer comprises silicon nitride;
the fifth inorganic layer comprises silicon oxide; and
the sixth inorganic layer comprises silicon nitride.
17. The thin film transistor of claim 16 , wherein:
the ninth inorganic layer comprises silicon nitride; and
the tenth inorganic layer comprises silicon oxide.
18. The thin film transistor of claim 15 , further comprising:
a layer of indium tin oxide disposed over the interlayer dielectric layer.
19. The thin film transistor of claim 18 , further comprising:
a polymer layer disposed over the interlayer dielectric layer and over the indium tin oxide layer.
20. The thin film transistor of claim 19 , further comprising:
a polyimide layer disposed over the indium tin oxide layer.
21. A transistor for controlling a pixel electrode, comprising:
a first interlayer dielectric layer, comprising silicon oxide;
a transition layer formed over the first interlayer dielectric layer, comprising silicon oxide and silicon nitride, wherein the transition layer comprises silicon oxide adjacent the first interlayer dielectric layer and silicon nitride adjacent the second interlayer dielectric layer; and
a second interlayer dielectric layer, comprising silicon nitride, wherein the pixel electrode is formed over the first interlayer dielectric layer, the transition layer, and the second interlayer dielectric layer.