Radiation detectors and methods of fabricating radiation detectors
Radiation detectors and methods of fabricating radiation detectors are provided. One method includes mechanically polishing at least a first surface of a semiconductor wafer using a polishing sequence including a plurality of polishing steps. The method also includes growing a passivation oxide layer on a top of the polished first surface and depositing patterned metal contacts on a top of the passivation oxide layer. The method further includes applying a protecting layer on the patterned deposited metal contacts, etching a second surface of the semiconductor and applying a monolithic cathode electrode on the etched second surface of the semiconductor. The method additionally includes removing the protecting layer from the patterned metal contacts on the first surface, wherein the patterned metal contacts are formed from one of (i) reactive metals and (ii) stiff-rigid metals for producing inter-band energy-levels in the passivation oxide layer.
1. A radiation detector comprising:
a semiconductor having energy-bands;
a passivation layer on a first surface of the semiconductor, wherein the first surface is formed by multiple steps of mechanical polishing without wet etching with a stoichiometric structure configured to create the passivation layer with a high-surface-resistivity;
pixelated anode electrodes having a MOS structure on the passivation layer, wherein gaps between the pixelated anode electrodes separate the pixelated anode electrodes from each other, the pixelated anode electrodes producing inter-band energy-levels in the passivation layer between the pixelated anode electrodes and the first surface based on (i) a mechanical stress between the pixelated anode electrodes and the passivation layer or (ii) at least a portion of the pixelated anodes penetrating the passivation layer, wherein a surface of the gaps include the passivation layer with the high-surface resistivity;
wherein the relative energy-position between the energy-bands of the semiconductor and the inter-band energy-levels of the passivation-layer is configured to adjust an electrical current between the semiconductor and the pixelated anode electrodes based on a bias applied between the pixelated anode electrodes and the semiconductor, wherein for a first bias the pixelated anode electrodes are configured to have a high conductivity and for an opposing second polarity the pixelated anode electrode are configured as blocking contacts; and
a monolithic cathode of a second surface of the semiconductor opposite the first surface.
2. The radiation detector of claim 1 , wherein the stoichiometric structure has no excess of an element of the semiconductor.
3. The radiation detector of claim 1 , further comprising a steering grid positioned within the gaps.
4. The radiation detector of claim 3 , wherein the steering grid is configured to be biased to have a positive electrical potential relative to the monolithic cathode increasing an electron drift between a first and second pixelated anode electrode, the first and second pixelated anode electrodes having an electrical potential that is higher than the positive electrical potential of the steering grid.
5. The radiation detector of claim 1 , wherein the passivation layer has a thickness of six nanometers.
6. A radiation detector for Nuclear Imaging, Single Photon Emission Computed Tomography, Positron Emission Tomography, and Computed Tomography comprising:
pixelated anode-electrodes having rectifying Metal-Oxide-Semiconductor (MOS) contacts, the rectifying MOS contacts include a CdZnTe (CZT) semiconductor plate having a first surface and a second surface, a passivation oxide layer on the first surface of the CZT semiconductor plate, and pixelated metal contacts on the passivation oxide layer, gaps separating the pixelated metal contacts from the passivation oxide layer,
wherein the pixelated metal contacts have a metal layer configured to produce inter-band energy levels in the passivation oxide layer based on a mechanical stress between the pixelated metal contacts and the passivation oxide layer, or at least a portion of the pixelated anodes penetrating the passivation layer,
wherein the passivation oxide layer has a thickness between three and six nanometers, the thickness of the passivation oxide layer is configured to ensure:
a surface resistivity that is similar to a bulk resistivity of the CZT semiconductor plate;
an encapsulation layer configured to protect the first surface; and
a reverse electrical current via the rectifying MOS contacts under reverse bias that is limited by quantum-tunneling;
wherein the thickness of the passivation oxide layer is further configured to allow formation of the inter-band energy levels in the passivation layer by the pixelated metal contacts, and the quantum-tunneling based on the inter-band energy levels configured to enhance forward electrical current via the rectifying MOS contacts under forward bias, the forward electrical current being higher than the reverse electrical current via the rectifying MOS contacts; and
a monolithic cathode on the second surface of the CZT semiconductor plate opposite to the first surface.