IP Library Granted Patent US 9,634,568
Granted Patent B2
US 9,634,568 · App. 14/770,626 · Granted Apr 25, 2017

Device for controlling and balancing currents for DC/DC converters

Inventors: Guillermo Garcia Soto (Massy, FR); Olivier Tarrade (Paris, FR)
Assignee: ALSTOM TECHNOLOGY LTD
H02M3/158H02M1/14H02M3/1584H02M2001/0009H02M2003/1586
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Quick Facts
Patent No.
US 9,634,568
App. No.
14/770,626
Granted
Apr 25, 2017
Kind
B2
Abstract

The invention provides a control device for regulating and balancing currents, for DC/DC converters, between first and second voltage sources, the device comprising: n converters (C 1 , C 2 , . . . Cn) that are connected in parallel to the first voltage source ( 11 ); n inductors (L 1 , L 2 , . . . Ln) that have their outlets connected to the second voltage source (R) via n connections; n current sensors ( 22 ) that are arranged on respective ones of the connections; and a single regulator system that has its inputs connected to respective ones of the n current sensors ( 22 ), and its output connected to the n converters (C 1 , C 2 , . . . Cn).

Claims (12)

1. A control device for regulating and balancing currents, for DC/DC converters, between first and second voltage sources, the device comprising:

n converters that are connected in parallel to the first voltage source;

n inductors that have their outlets connected to the second voltage source via n connections; and

n current sensors that are arranged on respective ones of the connections;

a single regulator system that has its inputs connected to respective ones of the n current sensors, and its output connected to the n converters, wherein the regulator system comprises:

a summing circuit for summing the currents output from the current sensors;

a PID block that receives the current output from the summing circuit;

a 1/n divider that receives the current output from the summing circuit and that delivers an average current;

n comparators for comparing the currents measured by the current sensors with the average current;

n proportional gain elements that are arranged at the outputs from the comparators;

n summing circuits for summing the outputs from the n proportional gain elements with the output from the PID block; and

a PWM block that receives the outputs from the n summing circuits and that delivers n interleaved channels.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2015
From: GARCIA SOTO, GUILLERMO; TARRADE, OLIVIER
To: ALSTOM TECHNOLOGY LTD
Reel/Frame 036521/0775 →
Priority Claims (1)
FR 13 51802 · Feb 28, 2013 · national
Continuity (1)
Related Publication 20160013721A1 · Jan 14, 2016