Method of operating digital-to-analog processing chains, corresponding device, apparatus and computer program product
A signal processing chain, such as an audio chain, produces an analog output signal from a digital input signal. The signal processing chain is operated by generating a first flag signal for the analog output signal and one or more second flag signals for the digital input signal. Each flag signal assumes a first level or a second level and is set to the first level when a signal from which the flag is generated has a value within an amplitude window. An amount the first flag signal for the analog output signal and the second flag signal for the digital input signal match each other may be calculated for issuing an alert flag which indicates an impaired operation of the signal processing chain.
1. A method of operating a signal processing chain producing an analog output signal from a digital input signal, the method comprising:
generating at least one first flag signal for the analog output signal and at least one second flag signal for the digital input signal, with generation of the at least one second flag signal being based on both the digital input signal and the at least one first flag signal, and with the at least one first and second flag signals having a first level and a second level and each being set to the first level when a respective signal from which the at least one first and second flags is generated has a value within an amplitude window; and
calculating, as a function of the at least one first flag signal and the at least one second flag signal, at least one of
an amount at least one first flag signal for the analog output signal and at least one second flag signal for the digital input signal match each other, and
an estimate of at least one operating parameter of the signal processing chain.
2. The method of claim 1 , further comprising sampling each first flag signal for the analog output signal at a same sampling frequency of the digital input signal.
3. The method of claim 1 , further comprising generating a second flag signal for the analog output signal for a combination of a plurality of output signal components, with the combination being an OR combination.
4. The method of claim 1 , further comprising calculating the amount the at least one first flag signal for the digital input signal and the at least one second flag signal match each other as at least one of the following:
a count of matches of the at least one first flag signal and the at least one second flag signal over a time frame;
a ratio of a number of matches of the at least one first flag signal and the at least one second flag signal to a total number of either type of the flag signals over the time frame; and
a variance of a number of matches of the at least one first flag signal and the at least one second flag signal over the time frame.
5. The method of claim 1 , further comprising:
calculating an amount the at least one first flag signal for the digital input signal and the at least one second flag signal match with each other; and
generating a performance check signal indicative of the amount, with the performance check signal comprising an alert flag issued when the amount falls below a performance quality threshold.
6. The method of claim 1 , further comprising calculating the estimate of at least one operating parameter of the signal processing chain as a target value based on a respective performance function by reducing a gradient of the respective performance function.
7. The method of claim 6 , wherein the at least one estimated operating parameter comprises at least one of a delay and a DC offset, and selecting the performance function as a difference of successful detections of the at least one first flag signal and the at least one second flag signal over a time frame.
8. The method of claim 6 , wherein the at least one estimated operating parameter includes a windowing threshold, and selecting the performance function as a difference of false detection events and missed detection events of the at least one first flag signal and the at least one second flag signal over a time frame.
9. The method of claim 1 , further comprising generating a performance check signal if the estimate of the at least one operating parameter lies outside a range for operation, with the performance check signal including an alert flag.
10. The method of claim 1 , further comprising feeding the estimate of the at least one operating parameter to a control loop acting on the digital input signal to compensate for system performance impairment.
11. The method of claim 1 , wherein generating the at least one second flag signal for the digital input signal comprises applying to the digital input signal at least one of a delay, a DC offset, and an amplitude window.
12. A device for operating a signal processing chain producing an analog output signal from a digital input signal, the device comprising:
at least one flag generating circuit configured to generate at least one first flag signal for the analog output signal and at least one second flag signal for the digital input signal, with generation of the at least one second flag signal being based on both the digital input signal and the at least one first flag signal, and with the at least one first and second flag signals having a first level and a second level and each being set to the first level when a respective signal from which the at least one first and second flags is generated has a value within an amplitude window; and
a processor configured to calculate, as a function of the at least one first flag signal and the at least one second flag signal, at least one of
an amount at least one first flag signal for the analog output signal and at least one second flag signal for the digital input signal match each other, and
an estimate of at least one operating parameter of the signal processing chain.
13. The device of claim 12 , wherein said processor is configured to sample each first flag signal for the analog output signal at a same sampling frequency of the digital input signal.
14. The device of claim 12 , wherein said at least one flag generating circuit is configured to generate a second flag signal for the analog output signal for a combination of a plurality of output signal components, with the combination being an OR combination.
15. The device of claim 12 , wherein said processor is configured to calculate the amount the at least one first flag signal for the digital input signal and the at least one second flag signal match each other as at least one of the following:
a count of matches of the at least one first flag signal and the at least one second flag signal over a time frame;
a ratio of a number of matches of the at least one first flag signal and the at least one second flag signal to a total number of either type of the flag signals over the time frame; and
a variance of a number of matches of the at least one first flag signal and the at least one second flag signal over the time frame.
16. The device of claim 12 , wherein said processor is configured to:
calculate an amount the at least one first flag signal for the digital input signal and the at least one second flag signal match with each other; and
generate a performance check signal indicative of the amount, with the performance check signal comprising an alert flag issued when the amount falls below a performance quality threshold.
17. The device of claim 12 , wherein said processor is configured to calculate the estimate of at least one operating parameter of the signal processing chain as a target value based on a respective performance function by reducing a gradient of the respective performance function.
18. An apparatus comprising:
a signal processing chain configured to drive at least one loudspeaker, and to produce an analog output signal from a digital input signal; and
a device configured to operate said signal processing chain and comprising
at least one flag generating circuit configured to generate at least one first flag signal for the analog output signal and at least one second flag signal for the digital input signal, with generation of the at least one second flag signal being based on both the digital input signal and the at least one first flag signal, and with the at least one first and second flag signals having a first level and a second level and each being set to the first level when a respective signal from which the at least one first and second flags is generated has a value within an amplitude window,
a processor configured to calculate, as a function of the at least one first flag signal and the at least one second flag signal, at least one of
an amount at least one first flag signal for the analog output signal and at least one second flag signal for the digital input signal match each other, and
an estimate of at least one operating parameter of the signal processing chain.
19. The apparatus of claim 18 , wherein said processor is configured to sample each first flag signal for the analog output signal at a same sampling frequency of the digital input signal.
20. The apparatus of claim 18 , wherein said at least one flag generating circuit is configured to generate a second flag signal for the analog output signal for a combination of a plurality of output signal components, with the combination being an OR combination.
21. The apparatus of claim 18 , wherein said processor is configured to calculate the amount the at least one first flag signal for the digital input signal and the at least one second flag signal match each other as at least one of the following:
a count of matches of the at least one first flag signal and the at least one second flag signal over a time frame;
a ratio of a number of matches of the at least one first flag signal and the at least one second flag signal to a total number of either type of the flag signals over the time frame; and
a variance of a number of matches of the at least one first flag signal and the at least one second flag signal over the time frame.
22. The apparatus of claim 18 , wherein said processor is configured to:
calculate an amount the at least one first flag signal for the digital input signal and the at least one second flag signal match with each other; and
generate a performance check signal indicative of the amount, with the performance check signal comprising an alert flag issued when the amount falls below a performance quality threshold.
23. The apparatus of claim 18 , wherein said processor is configured to calculate the estimate of at least one operating parameter of the signal processing chain as a target value based on a respective performance function by reducing a gradient of the respective performance function.
24. A non-transitory computer-readable medium to be loaded into a memory of at least one processor for causing the processor to operate a signal processing chain to produce an analog output signal from a digital input signal by:
generating at least one first flag signal for the analog output signal and at least one second flag signal for the digital input signal, with generation of the at least one second flag signal being based on both the digital input signal and the at least one first flag signal, and with the at least one first and second flag signals having a first level and a second level and each being set to the first level when a respective signal from which the at least one first and second flags is generated has a value within an amplitude window; and
calculating, as a function of the at least one first flag signal and the at least one second flag signal, at least one of
an amount at least one first flag signal for the analog output signal and at least one second flag signal for the digital input signal match each other, and
an estimate of at least one operating parameter of the signal processing chain.