IP Library › Granted Patent US 9,640,401
Granted Patent B2
US 9,640,401 · App. 15/188,472 · Granted May 2, 2017

Method of manufacturing a semiconductor device having a rear-side insert structure

Inventors: Johannes Georg Laven (Taufkirchen, DE); Hans-Joachim Schulze (Taufkirchen, DE); Anton Mauder (Kolbermoor, DE); Erich Griebl (Dorfen, DE)
Assignee: Infineon Technologies AG
H01L21/26513H01L21/0265H01L21/02532H01L21/02595H01L21/02598H01L21/02636H01L21/02639H01L21/02642H01L21/02647H01L21/02667H01L21/2251H01L21/2254H01L21/2257H01L21/26533H01L21/3065H01L21/30604H01L21/30625H01L21/324H01L21/3247H01L21/6835H01L23/544H01L29/04H01L29/0619H01L29/0623H01L29/0634H01L29/0649H01L29/0653H01L29/0661H01L29/0696H01L29/1095H01L29/16H01L29/36H01L29/66333H01L29/66348H01L29/7395H01L29/7397H01L29/8611H01L2221/6834H01L2221/68327H01L2223/5446H01L2223/54426H01L2924/0002
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,640,401
App. No.
15/188,472
Granted
May 2, 2017
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes forming a cavity in a first semiconductor layer formed on a semiconducting base layer, the cavity extending from a process surface of the first semiconductor layer at least down to the base layer, forming a recessed mask liner on a portion of a sidewall of the cavity distant to the process surface or a mask plug in a portion of the cavity distant to the process surface, and growing a second semiconductor layer on the process surface by epitaxy, the second semiconductor layer spanning the cavity.

Claims (29)

1. A method of manufacturing a semiconductor device, the method comprising:

forming a cavity in a first semiconductor layer formed on a semiconducting base layer, the cavity extending from a process surface of the first semiconductor layer at least down to the base layer;

forming a recessed mask liner on a portion of a sidewall of the cavity distant to the process surface or a mask plug in a portion of the cavity distant to the process surface;

growing a second semiconductor layer on the process surface by epitaxy, the second semiconductor layer spanning the cavity;

filling the cavity at least partly with a process material containing impurities; and

annealing the process material to diffuse out the impurities from the process material to form an impurity zone in the semiconductor body, the impurity zone directly adjoining the filled cavity and an impurity concentration of the impurities diffused into the impurity zone decreasing with increasing distance to the filled cavity.

2. The method of claim 1 , wherein the cavity is etched into the first semiconductor layer.

3. The method of claim 1 , further comprising:

capping the cavity by annealing the first semiconductor layer in a hydrogen-containing ambient before growing the second semiconductor layer, wherein material of the first semiconductor layer occludes the cavity.

4. The method of claim 1 , further comprising:

removing at least a portion of the base layer after growing the second semiconductor layer, wherein the cavity or a material in the cavity is exposed.

5. The method of claim 1 , wherein the process material is filled into a plurality of spatially separated cavities and the impurity zones adjoining the filled cavities form a contiguous layer.

6. The method of claim 5 , wherein an impurity concentration in the process material in the filled cavities varies in a vertical direction vertical to an interface between the first and second semiconductor layers.

7. The method of claim 1 , wherein the process material is polycrystalline semiconductor material, the method further comprising:

transforming the polycrystalline semiconductor material into single-crystalline semiconductor material.

8. The method of claim 1 , wherein the process material is single-crystalline semiconductor material.

9. A method of manufacturing a semiconductor device, the method comprising:

forming a cavity in a first semiconductor layer formed on a semiconducting base layer, the cavity extending from a process surface of the first semiconductor layer at least down to the base layer;

forming a recessed mask liner on a portion of a sidewall of the cavity distant to the process surface or a mask plug in a portion of the cavity distant to the process surface;

growing a second semiconductor layer on the process surface by epitaxy, the second semiconductor layer spanning the cavity; and

forming, in the cavity, a recombination structure with a recombination velocity of at least 1E5 cm/s or a phase change material.

10. A method of manufacturing a semiconductor device, the method comprising:

forming a cavity in a first semiconductor layer formed on a semiconducting base lay the cavity extending from a process surface of the first semiconductor layer at least down to the base layer;

forming a recessed mask liner on a portion of a sidewall of the cavity distant to the process surface or a mask plug in a portion of the cavity distant to the process surface;

growing a second semiconductor layer on the process surface by epitaxy, the second semiconductor layer spanning the cavity;

removing at least a portion of the base layer after growing the second semiconductor layer, wherein the cavity or a material in the cavity is exposed;

selectively removing material from an interior of the cavity;

implanting impurities through exposed sidewalls and bottoms of the exposed cavities; and

at least partly refilling the cavities.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2016
From: LAVEN, JOHANNES GEORG; SCHULZE, HANS-JOACHIM; MAUDER, ANTON; GRIEBL, ERICH
To: INFINEON TECHNOLOGIES AG
Reel/Frame 038975/0391 →
Continuity (2)
Division 14180924 · Feb 14, 2014
Related Publication 20160300719A1 · Oct 13, 2016