Semiconductor chip, flip chip package and wafer level package including the same

1. A semiconductor chip comprising:

a semiconductor substrate having an active face;

a first central pad and a second central pad arranged on a central region of the active face;

a first peripheral pad and a second peripheral pad arranged on an edge region of the active face;

a first pad line electrically connecting the first central pad with the first peripheral pad;

a second pad line electrically connecting the second central pad with the second peripheral pad; and

a passivation layer formed on the active face to cover the first pad line and the second pad line, the passivation layer having openings configured to expose the first central pad, the second central pad, the first peripheral pad and the second peripheral pad.

2. The semiconductor chip of claim 1 , wherein the first central pad is positioned adjacent to the second central pad, and the first peripheral pad is positioned adjacent to the second peripheral pad.

3. The semiconductor chip of claim 2 , wherein the first peripheral pad and the second peripheral pad are arranged in a row along a first direction substantially parallel to a side of the semiconductor substrate.

4. The semiconductor chip of claim 3 , wherein the first central pad and the second central pad are arranged in a row along the first direction.

5. The semiconductor chip of claim 3 , wherein the first central pad and the second central pad are arranged in a row along a second direction substantially perpendicular to the first direction.

6. The semiconductor chip of claim 5 , wherein the first central pad and the second central pad are arranged offset from each other in a first direction parallel to a side of the semiconductor substrate and a second direction perpendicular to the first direction.

7. The semiconductor chip of claim 1 , wherein the first central pad, the first peripheral pad and the first pad line have upper surfaces substantially coplanar with each other.

8. The semiconductor chip of claim 1 , wherein the second central pad, the second peripheral pad and the second pad line have upper surfaces substantially coplanar with each other.

9. A flip chip package comprising:

a semiconductor chip including a semiconductor substrate, a first central pad, a first peripheral pad, a first pad line electrically connecting the first central pad with the first peripheral pad, a second central pad, a second peripheral pad, and a second pad line electrically connecting the second central pad with the second peripheral pad, wherein the semiconductor substrate has an active face, the first central pad and the second central pad are arranged on a central region of the active face, and the first peripheral pad and the second peripheral pad are arranged on an edge region of the active face;

a package substrate disposed opposite to the active face of the semiconductor chip; and

first and second conductive bumps electrically connecting the semiconductor chip with the package substrate,

wherein the first conductive bump is disposed between the first peripheral pad and the package substrate, and the second conductive bump is disposed between the second peripheral pad and the package substrate.

10. The flip chip package of claim 9 , further comprising a molding member formed on the package substrate to cover the semiconductor chip.

11. The flip chip package of claim 9 , further comprising a second semiconductor chip stacked on the semiconductor chip, the second semiconductor chip electrically connected with the package substrate.

12. The flip chip package of claim 11 , further comprising a conductive wire electrically connecting the second semiconductor chip and the package substrate.

13. A flip chip package comprising:

a semiconductor chip including a semiconductor substrate, a first central pad, a first peripheral pad, a first pad line electrically connecting the first central pad with the first peripheral pad, a second central pad, a second peripheral pad, and a second pad line electrically connecting the second central pad with the second peripheral pad, wherein the semiconductor substrate has an active face, the first central pad and the second central pad are arranged on a central region of the active face, and the first peripheral pad and the second peripheral pad are arranged on an edge region of the active face;

a package substrate disposed opposite to the active face of the semiconductor chip; and

first and second conductive bumps electrically connecting the semiconductor chip with the package substrate,

wherein the first conductive bump is disposed between the first central pad and the package substrate, and the second conductive bump is disposed between the second peripheral pad and the package substrate.

14. A wafer level chip package comprising:

a semiconductor chip including a semiconductor substrate, a first central pad, a first peripheral pad, a first pad line electrically connecting the first central pad with the first peripheral pad, a second central pad, a second peripheral pad, a second pad line electrically connecting the second central pad with the second peripheral pad, wherein the semiconductor substrate has an active face, the first central pad and the second central pad are arranged on a central region of the active face, and the first peripheral pad and the second peripheral pad are arranged on an edge region of the active face;

a first redistribution layer extending from the first central pad or the first peripheral pad;

a second redistribution layer extending from the second central pad or the second peripheral pad; and

a first external terminal formed on the first redistribution layer and a second external terminal formed on the second redistribution layer.

15. The wafer level package of claim 14 , further comprising a passivation layer formed on the active face to cover the first pad line and the second pad line, wherein the passivation layer has openings to expose the first central pad, the second central pad, the first peripheral pad and the second peripheral pad, and wherein the first redistribution layer and the second redistribution layer are formed on the passivation layer.

16. The wafer level package of claim 14 , further comprising an insulating pattern formed on an upper surface of the passivation layer, the insulating pattern having openings configured to partially expose the first redistribution layer and the second redistribution layer.

17. The wafer level package of claim 14 , wherein the second redistribution layer is spaced apart from the second central pad and the second peripheral pad.