Start up method for switching converters using the same reference voltage in the error amplifier and PWM comparator
A switch-mode power supply is provided that includes a comparator for producing a pulse-width modulated (PWM) controller clock signal for controlling a power switch in the switch-mode power supply. The switch-mode power supply is configured to superimpose a DC-free version of a ramp voltage with an error voltage to produce a combined voltage. The comparator compares the combined voltage to a reference voltage to produce the PWM controller clock signal.
1. A circuit, comprising
an error amplifier configured to amplify a difference between a reference voltage and a scaled version of an output voltage for a switch-mode power supply to produce an error signal;
a resistor having a first terminal configured to receive the error signal and having a second terminal;
a ramp generator having a ramp output signal node coupled through a capacitor to the second terminal of the resistor; and
a comparator configured to produce a pulse-width modulated (PWM) controller output clock responsive to a comparison of the reference voltage to a voltage for the second terminal of the resistor.
2. The circuit of claim 1 , further comprising:
a digital-to-analog converter configured to provide the reference voltage responsive to a digital control word.
3. The circuit of claim 2 , further comprising:
a band gap reference configured to provide a band gap reference voltage as a power supply voltage to the digital-to-analog converter.
4. The circuit of claim 1 , wherein the ramp generator is a synchronous ramp generator configured to be responsive to a clock signal.
5. The circuit of claim 1 , further comprising a scaling circuit configured to scale the output voltage to form the scaled version of the output voltage.
6. The circuit of claim 5 , wherein the scaling circuit comprises a voltage divider circuit.
7. The circuit of claim 1 , further comprising a clamp circuit configured to clamp the voltage for the second terminal from rising above a maximum voltage level.
8. The circuit of claim 7 , wherein the clamp circuit comprises a diode.
9. The circuit of claim 1 , further comprising:
a power switch configured to be cycled on and off responsive to the PWM controller output clock.
10. The circuit of claim 9 , further comprising a power storage element configured to process an input voltage into the output voltage, wherein the power switch is further configured to control a current in the power storage element.
11. The circuit of claim 10 , wherein the power storage element is an inductor for a buck converter.
12. The circuit of claim 10 , wherein the power storage element is an inductor for a boost converter.
13. The circuit of claim 10 , wherein the power storage element is a secondary winding in a transformer for a flyback converter.
14. A method, comprising:
amplifying a difference between a scaled version of an output voltage from a switch-mode power supply and a reference voltage to produce an error voltage;
filtering a direct-current (DC) voltage component from a ramp voltage to produce a DC-free ramp voltage;
combining the DC-free ramp voltage with the error voltage to produce a combined voltage; and
producing a pulse-width-modulated controller clock signal responsive to a comparison of the combined voltage and the reference voltage.
15. The method of claim 14 , further comprising:
generating the ramp voltage responsive to a system clock signal.
16. The method of claim 14 , further comprising:
cycling a power switch in the switch-mode power supply responsive to the pulse-width-modulated controller clock signal.
17. The method of claim 14 , further comprising clamping the combined voltage to prevent the combined voltage from exceeding a maximum voltage level.
18. A circuit, comprising:
an error amplifier configured to amplify a difference between a reference voltage and a scaled version of an output voltage for a switch-mode power supply to produce an error amplifier voltage signal;
means for combining a direct-current (DC)-free version of a ramp voltage with the error amplifier voltage signal to produce a combined voltage; and
a comparator configured to produce a pulse-width modulated (PWM) controller output clock responsive to a comparison of the reference voltage to the combined voltage.
19. The circuit of claim 18 , further comprising:
a power switch configured to cycle on and off responsive to the PWM controller output clock.
20. The circuit of claim 18 , further comprising:
a synchronous ramp generator configured to provide the ramp voltage responsive to a system clock.