Testing and setting performance parameters in a semiconductor device and method therefor
A method of determining temperature ranges and setting performance parameters in a semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. The performance parameters may be set to improve speed parameters and/or decrease current consumption over a wide range of temperature ranges.
1. A method of setting performance parameters based on temperature in a plurality of semiconductor devices on a contiguous wafer, each semiconductor device including a temperature sensing circuit wherein the wafer includes a plurality of regions, each region including a plurality of semiconductor devices, comprising the steps of:
testing the operation of circuitry different than the temperature sensing circuit in one of the plurality of semiconductor devices in each region at a plurality of temperatures to determine a plurality of regional performance parameters corresponding to each one of the plurality of regions, each one of the plurality of temperatures in a corresponding one of a plurality of temperature ranges; wherein
each one of the plurality of semiconductor devices includes a performance parameter table and the method further includes the step of writing corresponding regional performance parameters to the performance parameter table for each one of the plurality of semiconductor devices for each corresponding region.
2. The method of claim 1 , wherein:
each one of the plurality of temperatures has a temperature value that is within a predetermined one of the plurality of temperature ranges set by the temperature sensing circuit.
3. The method of claim 2 , wherein:
the temperature value of each one of the plurality temperatures is essentially a midpoint of the predetermined one of the plurality of temperature ranges set by the temperature sensing circuit.
4. The method of claim 1 , wherein:
each region includes a centrally located semiconductor device and a plurality of adjacent semiconductor devices and only the centrally located semiconductor device is tested in the step of testing the operation of one of the plurality of semiconductor devices in each region.
5. The method of claim 1 , further including the step of:
dicing the wafer to separate the plurality of semiconductor devices.
6. The method of claim 5 , wherein:
the step of testing the operation and the step of writing corresponding regional performance parameters are performed before the step of dicing the wafer.
7. The method of claim 5 , wherein:
the step of testing the operation is performed before the step of dicing the wafer and the step of writing corresponding regional performance parameters is performed after the step of dicing the wafer.
8. The method of claim 5 , further including the step of:
packaging each one of the semiconductor devices.
9. The method of claim 8 , further including the step of:
the step of testing the operation is performed before the step of dicing the wafer and the step of writing corresponding regional performance parameters is performed after the step of packaging each one of the semiconductor devices.
10. A method of setting performance parameters based on temperature in a plurality of semiconductor devices on a contiguous wafer, each semiconductor device including a temperature sensing circuit wherein the wafer includes a plurality of regions, each region including a plurality of semiconductor devices, comprising the steps of:
testing the operation of circuitry different than the temperature sensing circuit in one of the plurality of semiconductor devices in each region at a plurality of temperatures to determine a plurality of regional performance parameters corresponding to each one of the plurality of regions, each one of the plurality of temperatures in a corresponding one of a plurality of temperature ranges; wherein
the step of testing includes determining the plurality of regional performance parameters corresponding to each one of the plurality of regions based on a desired operating specification for the plurality of semiconductor devices.
11. The method of claim 10 , wherein:
the operating specification is a timing specification.
12. The method of claim 11 , wherein:
the timing specification is an access time.
13. The method of claim 12 , wherein:
each of the plurality of semiconductor devices is a memory device.
14. The method of claim 11 , wherein.
the timing specification is a clock period.
15. The method of claim 14 , wherein:
each of the plurality of semiconductor devices is a processor.
16. The method of claim 10 , wherein:
the operating specification is a current specification.
17. The method of claim 16 , wherein:
the current specification is a standby current.
18. The method of claim 16 , wherein:
the current specification is an active current.
19. The method of claim 16 , wherein:
the current specification is an average current.