IP Library › Granted Patent US 9,646,714

Granted Patent B2

US 9,646,714 · App. 14/800,765 · Granted May 9, 2017

Shift register, semiconductor device, display device, and electronic device

Inventor: Atsushi Umezaki (Kanagawa, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

G11C19/184 G09G3/3266 G09G3/3677 G09G2310/0267 G09G2310/0275 G09G2310/0286 G09G2310/0289 G09G2320/02 G09G2320/043 G09G2330/021

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Quick Facts

Patent No.: US 9,646,714
App. No.: 14/800,765
Granted: May 9, 2017
Kind: B2

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Abstract

The invention provides a semiconductor device and a shift register, in which low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire. One of a source and a drain of the third transistor is connected to a second wire, the other of the source and the drain thereof is connected to the gate electrode of the second transistor, and a gate electrode thereof is connected to a fourth wire. One of a source and a drain of the fourth transistor is connected to the second wire, the other of the source and the drain thereof is connected to the sixth wire, and a gate electrode thereof is connected to the fourth wire.

Claims (141)

1. A semiconductor device comprising:

a shift register comprising first to fifth transistors,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,

wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor,

wherein a gate of the second transistor is electrically connected to a third wiring,

wherein one of a source and a drain of the third transistor is electrically connected to a power supply line,

wherein the other of the source and the drain of the third transistor is electrically connected to the second wiring,

wherein a gate of the third transistor is electrically connected to a fourth wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to the power supply line,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected a gate of the fourth transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring, and

wherein a clock signal is input to the fourth wiring.

2. The semiconductor device according to claim 1 ,

wherein one of a source and a drain of a sixth transistor is electrically connected the power supply line,

wherein the other of the source and the drain of the sixth transistor is electrically connected to the second wiring,

wherein a gate of the sixth transistor is electrically connected to a fifth wiring,

wherein one of a source and a drain of a seventh transistor is electrically connected to the power supply line,

wherein the other of the source and the drain of the seventh transistor is electrically connected to the gate of the first transistor, and

wherein a gate of the seventh transistor is electrically connected to the fifth wiring.

3. A semiconductor device comprising:

a shift register comprising first to seventh transistors,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and a gate of the first transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fourth transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor and a gate of the fifth transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fourth transistor and the other of the source and the drain of the seventh transistor, and

wherein a clock signal is input to the other of the source and the drain of the fifth transistor.

4. The semiconductor device according to claim 3 , wherein the other of the source and the drain of the sixth transistor is electrically connected a gate of the sixth transistor.

5. The semiconductor device according to claim 4 ,

wherein the shift register comprises a first capacitor,

wherein a first electrode of the first capacitor is electrically connected to the other of the source and the drain of the second transistor, and

wherein a second electrode of the first capacitor is electrically connected to the gate of the fifth transistor.

6. The semiconductor device according to claim 4 ,

wherein the shift register comprises a second capacitor,

wherein a first electrode of the second capacitor is electrically connected to the gate of the first transistor, and

wherein a second electrode of the second capacitor is electrically connected to the one of the source and the drain of the first transistor.

7. The semiconductor device according to claim 3 ,

wherein the other of the source and the drain of the sixth transistor is electrically connected a gate of the sixth transistor.

8. The semiconductor device according to claim 7 ,

wherein the shift register comprises a first capacitor,

wherein a first electrode of the first capacitor is electrically connected to the other of the source and the drain of the second transistor, and

wherein a second electrode of the first capacitor is electrically connected to the gate of the fifth transistor.

9. The semiconductor device according to claim 7 ,

wherein the shift register comprises a second capacitor,

wherein a first electrode of the second capacitor is electrically connected to the gate of the first transistor, and

wherein a second electrode of the second capacitor is electrically connected to the one of the source and the drain of the first transistor.

10. The semiconductor device according to claim 3 ,

wherein the shift register comprises a first capacitor,

wherein a first electrode of the first capacitor is electrically connected to the other of the source and the drain of the second transistor, and

wherein a second electrode of the first capacitor is electrically connected to the gate of the fifth transistor.

11. The semiconductor device according to claim 3 ,

wherein the shift register comprises a first capacitor,

wherein a first electrode of the first capacitor is electrically connected to the other of the source and the drain of the second transistor, and

wherein a second electrode of the first capacitor is electrically connected to the gate of the fifth transistor.

12. The semiconductor device according to claim 3 ,

wherein the shift register comprises a second capacitor,

wherein a first electrode of the second capacitor is electrically connected to the gate of the first transistor, and

wherein a second electrode of the second capacitor is electrically connected to the one of the source and the drain of the first transistor.

13. The semiconductor device according to claim 3 , wherein a potential is supplied to the other of the source and the drain of the sixth transistor.

14. The semiconductor device according to claim 3 ,

wherein the shift register comprises a second capacitor,

wherein a first electrode of the second capacitor is electrically connected to the gate of the first transistor, and

wherein a second electrode of the second capacitor is electrically connected to the one of the source and the drain of the first transistor.

15. A semiconductor device comprising:

a shift register comprising first to seventh transistors,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, a gate of the first transistor and a gate of the seventh transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the third transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fourth transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor and a gate of the fifth transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to a gate of the sixth transistor,

wherein the one of the source and the drain of the first transistor is electrically connected to a pixel,

wherein a first clock signal is input to the other of the source and the drain of the first transistor, and

wherein a second clock signal is input to the other of the source and the drain of the fifth transistor, the second clock signal being different from the first clock signal.

16. The semiconductor device according to claim 15 , wherein the gate of the sixth transistor is electrically connected to a power source.

17. A semiconductor device comprising:

a shift register comprising first to fourteenth transistors,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the third transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the fourth transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor and a gate of the fifth transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to a gate of the sixth transistor,

wherein the one of the source and the drain of the first transistor is electrically connected to a pixel,

wherein a first clock signal is input to the other of the source and the drain of the first transistor,

wherein a second clock signal is input to the other of the source and the drain of the fifth transistor, the second clock signal being different from the first clock signal,

wherein one of a source and a drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor,

wherein one of a source and a drain of the tenth transistor is electrically connected to one of a source and a drain of the eleventh transistor, a gate of the eighth transistor and a gate of the fourteenth transistor,

wherein the other of the source and the drain of the tenth transistor is electrically connected to a gate of the tenth transistor,

wherein one of a source and a drain of the twelfth transistor is electrically connected to a gate of the eleventh transistor,

wherein the other of the source and the drain of the twelfth transistor is electrically connected to a gate of the ninth transistor,

wherein one of a source and a drain of the thirteenth transistor is electrically connected to one of a source and a drain of the fourteenth transistor and a gate of the twelfth transistor,

wherein the other of the source and the drain of the thirteenth transistor is electrically connected to a gate of the thirteenth transistor,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the other of the source and the drain of the eleventh transistor and the other of the source and the drain of the fourteenth transistor,

wherein the one of the source and the drain of the eighth transistor is electrically connected to a pixel,

wherein the gate of the tenth transistor is electrically connected to the one of the source and the drain of the first transistor.

18. The semiconductor device according to claim 17 , wherein the gate of the sixth transistor is electrically connected to a power source.

19. A semiconductor device comprising:

a shift register comprising first to seventh transistors,

wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,

wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor, a gate of the first transistor and a gate of the seventh transistor,

wherein the other of the source and the drain of the third transistor is directly connected to a gate of the third transistor,

wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the fourth transistor,

wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the second transistor,

wherein one of a source and a drain of the sixth transistor is directly connected to one of a source and a drain of the seventh transistor and a gate of the fifth transistor,

wherein the other of the source and the drain of the sixth transistor is directly connected to a gate of the sixth transistor,

wherein the other of the source and the drain of the second transistor is directly connected to the other of the source and the drain of the fourth transistor and the other of the source and the drain of the seventh transistor,

wherein the one of the source and the drain of the first transistor is directly connected to a pixel,

wherein a first clock signal is input to the other of the source and the drain of the first transistor, and

wherein a second clock signal is input to the other of the source and the drain of the fifth transistor, the second clock signal being different from the first clock signal.

20. The semiconductor device according to claim 19 , wherein the gate of the sixth transistor is electrically connected to a power source.

21. A semiconductor device comprising: