Ceramic substrate including thin film multilayer surface conductor
View Patent ↗A ceramic substrate comprises a plurality of ceramic sheets, a plurality of inner conductive layers, a plurality of vias, and an upper conductive layer. The ceramic sheets are stacked one on top of another and include a top ceramic sheet. The inner conductive layers include electrically conductive material that forms electrically conductive features on an upper surface of each ceramic sheet excluding the top ceramic sheet. The vias are formed in each of the ceramic sheets with each via being filled with electrically conductive material. The upper conductive layer includes electrically conductive material that forms electrically conductive features on an upper surface of the top ceramic sheet. The upper conductive layer is constructed from a stack of four sublayers. A first sublayer is formed from titanium. A second sublayer is formed from copper. A third sublayer is formed from platinum. A fourth sublayer is formed from gold.
1. A ceramic substrate comprising:
a plurality of ceramic sheets stacked one on top of another, the ceramic sheets including a top ceramic sheet;
a plurality of inner conductive layers forming electrically conductive features on an upper surface of each ceramic sheet excluding the top ceramic sheet, each inner conductive layer formed from an electrically conductive material;
a plurality of vias formed in each of the ceramic sheets, each via filled with the electrically conductive material;
a plurality of caps positioned on the upper surface of the top ceramic sheet, each cap formed from the electrically conductive material, covering one via on the top ceramic sheet, and having a diameter greater than a diameter of the via; and
an upper conductive layer forming electrically conductive features on an upper surface of the top ceramic sheet, the upper conductive layer constructed from one or more thin film sublayers.
2. A ceramic substrate comprising:
a plurality of ceramic sheets stacked one on top of another, the ceramic sheets including a top ceramic sheet;
a plurality of inner conductive layers forming electrically conductive features on an upper surface of each ceramic sheet excluding the top ceramic sheet, each inner conductive layer formed from an electrically conductive material;
a plurality of vias formed in each of the ceramic sheets, each via filled with the electrically conductive material;
a plurality of caps positioned on the upper surface of the top ceramic sheet, each cap formed from the electrically conductive material, covering one via in the top ceramic sheet, and having a diameter greater than a diameter of the via; and
an upper conductive layer forming electrically conductive features on an upper surface of the top ceramic sheet, the upper conductive layer constructed from a stack of sublayers including:
a first sublayer formed from titanium having a thickness ranging from 0 micrometers (μm) to 0.4 μm,
a second sublayer formed from copper having a thickness ranging from 1 μm to 18 μm,
a third sublayer formed from platinum having a thickness ranging from 1 μm to 4 μm, and
a fourth sublayer formed from gold having a thickness ranging from 0.1 μm to 0.5 μm,
wherein the first sublayer contacts the upper surface of the top ceramic sheet and hermetically seals the caps in the top ceramic sheet and the fourth sublayer is configured to receive electrical connectors from electronic circuitry placed on the ceramic substrate.
3. The ceramic substrate of claim 1 , wherein the upper conductive layer covers and hermetically seals each cap.
4. The ceramic substrate of claim 1 , wherein the one or more thin film sublayers includes a stack of sublayers including a first sublayer formed from titanium, a second sublayer formed from copper, a third sublayer formed from platinum, and a fourth sublayer formed from gold, wherein the first sublayer contacts the upper surface of the top ceramic sheet and electrically connects to the vias in the top ceramic sheet and the fourth sublayer is configured to receive electrical connectors from electronic circuitry placed on the ceramic substrate.
5. The ceramic substrate of claim 4 , wherein the first sublayer has a thickness ranging from 0 micrometers (μm) to 0.4 μm.
6. The ceramic substrate of claim 4 , wherein the second sublayer has a thickness ranging from 1 μm to 18 μm.
7. The ceramic substrate of claim 4 , wherein the third sublayer has a thickness ranging from 1 μm to 4 μm.
8. The ceramic substrate of claim 4 , wherein the fourth sublayer has a thickness ranging from 0.1 μm to 0.5 μm.
9. The ceramic substrate of claim 1 , further comprising a lower conductive layer forming electrically conductive features on a lower surface of a bottom ceramic sheet, the lower conductive layer constructed from one or more thin film sublayers.
10. The ceramic substrate of claim 9 , wherein the one or more thin film sublayers of the lower conductive layer includes a stack of sublayers including a first sublayer formed from titanium, a second sublayer formed from copper, a third sublayer formed from platinum, and a fourth sublayer formed from gold, wherein the first sublayer contacts the upper surface of the bottom ceramic sheet and electrically connects to the vias in the bottom ceramic sheet and the fourth sublayer is configured to receive electrical connectors from electronic circuitry placed on the bottom surface of the ceramic substrate.
11. A ceramic substrate comprising:
a plurality of ceramic sheets stacked one on top of another, the ceramic sheets including a top ceramic sheet;
a plurality of inner conductive layers forming electrically conductive features on an upper surface of each ceramic sheet excluding the top ceramic sheet, each inner conductive layer formed from an electrically conductive material;
a plurality of vias formed in each of the ceramic sheets, each via filled with the electrically conductive material;
a plurality of caps positioned on the upper surface of the top ceramic sheet, each cap formed from the electrically conductive material, covering one via in the top ceramic sheet, and having a diameter greater than a diameter of the via; and
an upper conductive layer forming electrically conductive features on an upper surface of the top ceramic sheet, the upper conductive layer constructed from a stack of sublayers including a first sublayer formed from titanium, a second sublayer formed from copper, a third sublayer formed from platinum, and a fourth sublayer formed from gold, wherein the first sublayer contacts the upper surface of the top ceramic sheet and hermetically seals the caps in the top ceramic sheet and the fourth sublayer is configured to receive electrical connectors from electronic circuitry placed on the ceramic substrate.
12. The ceramic substrate of claim 11 , wherein the first sublayer has a thickness ranging from 0 micrometers (μm) to 0.4 μm.
13. The ceramic substrate of claim 11 , wherein the second sublayer has a thickness ranging from 1 μm to 18 μm.
14. The ceramic substrate of claim 11 , wherein the third sublayer has a thickness ranging from 1 μm to 4 μm.
15. The ceramic substrate of claim 11 , wherein the fourth sublayer has a thickness ranging from 0.1 μm to 0.5 μm.