IP Library › Granted Patent US 9,653,490

Granted Patent B2

US 9,653,490 · App. 14/623,193 · Granted May 16, 2017

Semiconductor device and electronic device

Inventor: Atsushi Umezaki (Kanagawa, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H01L27/124 G09G3/20 H01L27/1225 H01L29/1033 H01L29/7869 H03K19/00346 G09G3/3266 G09G3/3674 G09G2310/0267 G09G2310/0286 G11C19/28

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Quick Facts

Patent No.: US 9,653,490
App. No.: 14/623,193
Granted: May 16, 2017
Kind: B2

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Abstract

To provide a novel shift register. Transistors 101 to 104 are provided. A first terminal of the transistor 101 is connected to a wiring 111 and a second terminal of the transistor 101 is connected to a wiring 112 . A first terminal of the transistor 102 is connected to a wiring 113 and a second terminal of the transistor 102 is connected to the wiring 112 . A first terminal of the transistor 103 is connected to the wiring 113 and a gate of the transistor 103 is connected to the wiring 111 or a wiring 119 . A first terminal of the transistor 104 is connected to a second terminal of the transistor 103 , a second terminal of the transistor 104 is connected to a gate of the transistor 101 , and a gate of the transistor 104 is connected to a gate of the transistor 102.

Claims (73)

1. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, and a fourth transistor; and

a first wiring and a second wiring,

wherein the first transistor, the second transistor, the third transistor, and the fourth transistor have the same conductivity type,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the first transistor and a gate of the third transistor are electrically connected to the first wiring,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the other of the source and the drain of the second transistor and one of a source and a drain of the third transistor are electrically connected to the second wiring,

wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor, and

wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor.

2. The semiconductor device according to claim 1 , wherein a ratio of a channel width to a channel length of the fourth transistor is higher than a ratio of a channel width to a channel length of the third transistor.

3. The semiconductor device according to claim 1 ,

wherein the third transistor comprises a first semiconductor layer and a first gate electrode,

wherein the fourth transistor comprises a second semiconductor layer and a second gate electrode, and

wherein an area where the second semiconductor layer and the second gate electrode overlap with each other is larger than an area where the first semiconductor layer and the first gate electrode overlap with each other.

4. The semiconductor device according to claim 1 , wherein a channel formation region of at least one of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises an oxide semiconductor.

5. The semiconductor device according to claim 1 ,

wherein the first wiring is configured to supply a clock signal to the other of the source and the drain of the first transistor and the gate of the third transistor, and

wherein the second wiring is configured to supply a voltage to the other of the source and the drain of the second transistor and the one of the source and the drain of the third transistor.

6. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, and a fourth transistor; and

a first wiring, a second wiring, and a third wiring,

wherein the first transistor, the second transistor, the third transistor, and the fourth transistor have the same conductivity type,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to the first wiring,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the other of the source and the drain of the second transistor and one of a source and a drain of the third transistor are electrically connected to the second wiring,

wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor,

wherein a gate of the third transistor is electrically connected to the third wiring, and

wherein the gate of the third transistor is not electrically connected to the gate of the fourth transistor.

7. The semiconductor device according to claim 6 , wherein a ratio of a channel width to a channel length of the fourth transistor is higher than a ratio of a channel width to a channel length of the third transistor.

8. The semiconductor device according to claim 6 ,

wherein the third transistor comprises a first semiconductor layer and a first gate electrode,

wherein the fourth transistor comprises a second semiconductor layer and a second gate electrode, and

9. The semiconductor device according to claim 6 , wherein a channel formation region of at least one of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises an oxide semiconductor.

10. The semiconductor device according to claim 6 ,

wherein the first wiring is configured to supply a first clock signal to the other of the source and the drain of the first transistor,

wherein the second wiring is configured to supply a voltage to the other of the source and the drain of the second transistor and the one of the source and the drain of the third transistor, and

wherein the third wiring is configured to supply a second clock signal to the gate of the third transistor.

11. The semiconductor device according to claim 6 , wherein different signals are input to the gate of the third transistor and the gate of the fourth transistor.

12. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; and

a first wiring, a second wiring, a third wiring, and a fourth wiring,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor have the same conductivity type,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the first transistor and a gate of the third transistor are electrically connected to the first wiring,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the other of the source and the drain of the second transistor and one of a source and a drain of the third transistor are electrically connected to the second wiring,

wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor, one of a source and a drain of the sixth transistor, and one of a source and a drain of the seventh transistor,

wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the seventh transistor,

wherein the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring, and

wherein a gate of the sixth transistor is electrically connected to the third wiring.

13. The semiconductor device according to claim 12 , wherein a ratio of a channel width to a channel length of the fourth transistor is higher than a ratio of a channel width to a channel length of the third transistor.

14. The semiconductor device according to claim 12 ,

wherein the third transistor comprises a first semiconductor layer and a first gate electrode,

wherein the fourth transistor comprises a second semiconductor layer and a second gate electrode, and

15. The semiconductor device according to claim 12 , wherein a channel formation region of at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor comprises an oxide semiconductor.

16. The semiconductor device according to claim 12 ,

wherein the first wiring is configured to supply a first clock signal to the other of the source and the drain of the first transistor,

wherein the second wiring is configured to supply a voltage to the other of the source and the drain of the second transistor and the one of the source and the drain of the third transistor,

wherein the third wiring is configured to supply a second clock signal to the gate of the sixth transistor, and

wherein the fourth wiring is configured to supply a start pulse to the other of the source and the drain of the fourth transistor.

17. The semiconductor device according to claim 12 , wherein a gate of the fifth transistor is electrically connected to the third wiring.

18. The semiconductor device according to claim 12 , wherein a gate of the fifth transistor is electrically connected to the fourth wiring.

19. The semiconductor device according to claim 12 , wherein the other of the source and the drain of the sixth transistor is electrically connected to the third wiring.

20. The semiconductor device according to claim 12 , further comprising a fifth wiring,

wherein the other of the source and the drain of the sixth transistor is electrically connected to the fifth wiring.

21. The semiconductor device according to claim 12 , wherein the other of the source and the drain of the seventh transistor is electrically connected to the second wiring.

22. The semiconductor device according to claim 12 , wherein the other of the source and the drain of the seventh transistor is electrically connected to the third wiring.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2015

From: UMEZAKI, ATSUSHI

To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Reel/Frame 034967/0726 →

Priority Claims (1)

JP 2014-031501 · Feb 21, 2014 · national

Continuity (1)

Related Publication 20150243678A1 · Aug 27, 2015