Integrated circuit device having III-V compound semiconductor region comprising magnesium and N-type impurity and overlying III-V compound semiconductor layer formed without Cp2Mg precursor
A method includes epitaxially growing a first III-V compound semiconductor, wherein the first III-V compound semiconductor is of p-type. The first III-V compound semiconductor is grown using precursors including a first precursor comprising Cp2Mg, and a second precursor comprising a donor impurity. A second III-V compound semiconductor is grown overlying and contacting the first III-V compound semiconductor. The second III-V compound semiconductor is of n-type.
1. An integrated circuit device comprising:
a semiconductor substrate;
Shallow Trench Isolation (STI) regions in the semiconductor substrate;
a first III-V compound semiconductor region comprising a first portion higher than top surfaces of the STI regions, wherein the first portion comprises magnesium and a donor impurity;
a second III-V compound semiconductor layer comprising a first portion overlying and contacting the first III-V compound semiconductor region, wherein the second III-V compound semiconductor layer is of n-type;
a gate dielectric overlapping the second III-V compound semiconductor layer; and
a gate electrode over the gate dielectric.
2. The integrated circuit device of claim 1 , wherein the donor impurity is selected from the group consisting essentially of silicon, germanium, selenium, tellurium, and combinations thereof.
3. The integrated circuit device of claim 1 , wherein the first III-V compound semiconductor region has a net impurity concentration of p-type.
4. The integrated circuit device of claim 1 further comprising a source region and a drain region connected to opposite ends of the second III-V compound semiconductor layer, wherein the source region and the drain region are of n-type, wherein the second III-V compound semiconductor layer forms a channel region of an accumulation-mode Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), with the accumulation-mode MOSFET comprising the gate dielectric, the gate electrode, the source region, and the drain region.
5. The integrated circuit device of claim 1 , wherein the first portion of the first III-V compound semiconductor region has substantially vertical sidewalls.
6. The integrated circuit device of claim 1 , wherein the second III-V compound semiconductor layer is free from the donor impurity.
7. The integrated circuit device of claim 1 further comprising:
a source region and a drain region connected to opposite ends of the second III-V compound semiconductor layer, wherein the source region and the drain region are of n-type, wherein the second III-V compound semiconductor layer forms a channel region of an accumulation-mode Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), with the accumulation-mode MOSFET comprising the gate dielectric, the gate electrode, the source region, and the drain region.
8. The integrated circuit device of claim 1 , wherein the first III-V compound semiconductor region further comprises a second portion between, and coplanar with, opposite portions of the STI regions.
9. The integrated circuit device of claim 1 , wherein the second III-V compound semiconductor layer further comprises a second portion on a sidewall of the first portion of the first III-V compound semiconductor region.
10. The integrated circuit device of claim 1 , wherein the second III-V compound semiconductor layer is free from portions on sidewalls of the first portion of the first III-V compound semiconductor region.
11. The integrated circuit device of claim 1 , wherein the second III-V compound semiconductor layer is of n-type.
12. An integrated circuit device comprising:
a first In-V compound semiconductor region comprising magnesium and a donor impurity selected from the group consisting essentially of silicon, germanium, selenium, tellurium, and combinations thereof, wherein the first In-V compound semiconductor region is of p-type; and
a second In-V compound semiconductor layer overlying and contacting the first In-V compound semiconductor region, wherein the second In-V compound semiconductor layer is free from magnesium, and the second In-V compound semiconductor layer is of n-type;
a gate dielectric over the second In-V compound semiconductor layer;
a gate electrode over the gate dielectric; and
a source region and a drain region connected to opposite ends of the second In-V compound semiconductor layer, wherein the source region and the drain region are of n-type, wherein the second In-V compound semiconductor layer forms a channel region of an accumulation-mode Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), with the accumulation-mode MOSFET comprising the gate dielectric, the gate electrode, the source region, and the drain region.
13. The integrated circuit device of claim 12 further comprising:
a semiconductor substrate; and
Shallow Trench Isolation (STI) regions in the semiconductor substrate, wherein the first In-V compound semiconductor region extends into a recess between two opposite portions of the STI regions.
14. The integrated circuit device of claim 13 , wherein the magnesium and the donor impurity extend into the recess.
15. The integrated circuit device of claim 13 , wherein the second In-V compound semiconductor layer further extends on a sidewall of the first In-V compound semiconductor region.
16. The integrated circuit device of claim 13 , wherein the semiconductor substrate is a silicon substrate.
17. An integrated circuit device comprising:
a semiconductor substrate;
Shallow Trench Isolation (STI) regions in the semiconductor substrate;
a first In-V compound semiconductor region comprising magnesium and a donor impurity selected from the group consisting essentially of silicon, germanium, selenium, tellurium, and combinations thereof, wherein the first In-V compound semiconductor region is of p-type, wherein the first In-V compound semiconductor region extends into a recess between two opposite portions of the STI regions;
a second In-V compound semiconductor layer overlying and contacting the first In-V compound semiconductor region, wherein the second In-V compound semiconductor layer is free from magnesium, and the second In-V compound semiconductor layer is of n-type;
a gate dielectric over the second In-V compound semiconductor layer;
a gate electrode over the gate dielectric; and
a source region and a drain region connected to opposite ends of the second In-V compound semiconductor layer, wherein the source region and the drain region are of n-type, wherein the second In-V compound semiconductor layer forms a channel region of an accumulation-mode Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), with the accumulation-mode MOSFET comprising the gate dielectric, the gate electrode, the source region, and the drain region.
18. The integrated circuit device of claim 17 , wherein the second In-V compound semiconductor layer comprises an additional donor impurity.
19. The integrated circuit device of claim 17 , wherein the magnesium and the donor impurity extend into the recess.
20. The integrated circuit device of claim 17 , wherein the second In-V compound semiconductor layer contacts a sidewall and a top surface of the first In-V compound semiconductor region.