IP Library › Granted Patent US 9,660,100
Granted Patent B2
US 9,660,100 · App. 15/011,833 · Granted May 23, 2017

Semiconductor device and method for manufacturing the same

Inventor: Yutaka Okazaki (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/7869H01L29/66969H01L21/76805H01L2221/1031
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Quick Facts
Patent No.
US 9,660,100
App. No.
15/011,833
Granted
May 23, 2017
Kind
B2
Abstract

A semiconductor device is formed in such a manner that a first insulator, a first oxide semiconductor, and a first conductor are formed; the first conductor is processed to form a second conductor; the first oxide semiconductor is processed to form a second oxide semiconductor; a second insulator is formed over the second conductor; a third insulator is formed over the second insulator; a fourth insulator is formed over the third insulator; the fourth insulator, the third insulator, the second insulator, and the second conductor are selectively processed to partly expose the second oxide semiconductor; a fifth insulator is formed over the second oxide semiconductor and the fourth insulator; and a third conductor is formed over the fifth insulator and then chemical mechanical polishing treatment is performed to expose a top surface of the fourth insulator.

Claims (94)

1. A method for manufacturing a semiconductor device comprising the steps of:

forming a first insulator;

forming a first semiconductor over the first insulator;

forming a first conductor over the first semiconductor;

patterning the first conductor to form a second conductor;

patterning the first semiconductor to form a second semiconductor;

forming a second insulator over the second conductor;

forming a third insulator over the second insulator;

forming a fourth insulator over the third insulator;

removing a part of the fourth insulator to expose the third insulator;

removing a part of the third insulator to expose the second insulator;

removing a part of the second insulator to expose the second conductor;

removing a part of the second conductor to expose the second semiconductor;

forming a fifth insulator over the second semiconductor and the fourth insulator;

forming a third conductor over the fifth insulator; and

performing chemical mechanical polishing treatment to expose a top surface of the fourth insulator.

2. The method for manufacturing a semiconductor device according to claim 1 , further comprising the steps of:

forming a third oxide semiconductor over the fifth insulator before the step of forming the third conductor.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein the first semiconductor includes two to four stacked oxide semiconductors.

4. The method for manufacturing a semiconductor device according claim 1 ,

wherein a surface of the second insulator is planarized by chemical mechanical polishing treatment.

5. The method for manufacturing a semiconductor device according to claim 1 , wherein the third conductor includes at least two stacked conductors.

6. The method for manufacturing a semiconductor device according to claim 1 , wherein the third conductor includes copper.

7. The method for manufacturing a semiconductor device according claim 1 ,

wherein the first semiconductor is a first oxide semiconductor, and

wherein the second semiconductor is a second oxide semiconductor.

8. A method for manufacturing a semiconductor device comprising the steps of:

forming a first insulator;

forming a first semiconductor over the first insulator;

patterning the first semiconductor to form a second semiconductor;

forming a first conductor over the second semiconductor;

patterning the first conductor to form a second conductor;

forming a second insulator over the second conductor;

forming a third insulator over the second insulator;

forming a fourth insulator over the third insulator;

removing a part of the fourth insulator to expose the third insulator;

removing a part of the third insulator to expose the second insulator;

removing a part of the second insulator to expose the second conductor;

removing a part of the second conductor to expose the second semiconductor;

forming a fifth insulator over the second semiconductor and the fourth insulator;

forming a third conductor over the fifth insulator; and

performing chemical mechanical polishing treatment to expose a top surface of the fourth insulator.

9. The method for manufacturing a semiconductor device according to claim 8 , further comprising the steps of:

forming a third oxide semiconductor over the fifth insulator before the step of forming the third conductor.

10. The method for manufacturing a semiconductor device according to claim 8 , wherein the first semiconductor includes two to four stacked oxide semiconductors.

11. The method for manufacturing a semiconductor device according claim 8 , wherein a surface of the second insulator is planarized by chemical mechanical polishing treatment.

12. The method for manufacturing a semiconductor device according to claim 8 , wherein the third conductor includes at least two stacked conductors.

13. The method for manufacturing a semiconductor device according to claim 8 , wherein the third conductor includes copper.

14. The method for manufacturing a semiconductor device according to claim 8 ,

wherein the first semiconductor is a first oxide semiconductor, and

wherein the second semiconductor is a second oxide semiconductor.

15. A method for manufacturing a semiconductor device comprising the steps of:

forming a first insulator;

forming a first semiconductor over the first insulator;

forming a first conductor over the first semiconductor;

patterning the first conductor to form a second conductor;

patterning the first semiconductor to form a second semiconductor;

forming a second insulator over the second conductor;

forming a third insulator over the second insulator;

removing a part of the third insulator to expose the second insulator;

removing a part of the second insulator to expose the second conductor;

removing a part of the second conductor to expose the second semiconductor;

forming a sacrifice layer over the second semiconductor and the third insulator;

performing chemical mechanical polishing treatment to expose a top surface of the third insulator;

forming a fourth insulator over the third insulator and the sacrifice layer; removing a part of the fourth insulator to expose a top surface of the sacrifice layer;

removing the sacrifice layer to partly expose the second semiconductor;

forming a fifth insulator over the second semiconductor and the fourth insulator;

forming a third conductor over the fifth insulator; and

performing chemical mechanical polishing treatment to expose a top surface of the fourth insulator.

16. The method for manufacturing a semiconductor device according to claim 15 , further comprising the steps of:

forming a third oxide semiconductor over the fifth insulator before the steps of forming the third conductor.

17. The method for manufacturing a semiconductor device according to claim 15 , wherein the first semiconductor includes two to four stacked oxide semiconductors.

18. The method for manufacturing a semiconductor device according claim 15 ,

wherein a surface of the second insulator is planarized by chemical mechanical polishing treatment.

19. The method for manufacturing a semiconductor device according to claim 15 , wherein the third conductor includes at least two stacked conductors.

20. The method for manufacturing a semiconductor device according to claim 15 , wherein the third conductor includes copper.

21. A semiconductor device comprising:

a first insulator over a substrate;

a first semiconductor over the first insulator;

a second semiconductor over the first semiconductor;

a first conductor and a second conductor over the second semiconductor;

a second insulator over the first insulator, the first conductor, and the second conductor;

a third insulator over the second insulator;

a fourth insulator over the third insulator;

a third semiconductor over the second semiconductor;

a fifth insulator over the third semiconductor; and

a third conductor over the fifth insulator,

wherein an area of a top surface of the third conductor is larger than an area of a bottom surface of the third conductor, and

wherein a relative dielectric constant of the third insulator is higher than a relative dielectric constant of the second insulator.

22. The semiconductor device according to claim 21 , wherein the third conductor includes at least two stacked conductors.

23. The semiconductor device according to claim 21 , wherein the third conductor includes copper.

24. The method for manufacturing a semiconductor device according to claim 15 ,

wherein the first semiconductor is a first oxide semiconductor, and

wherein the second semiconductor is a second oxide semiconductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: OKAZAKI, YUTAKA
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 037668/0692 →
Priority Claims (1)
JP 2015-022392 · Feb 6, 2015 · national
Continuity (1)
Related Publication 20160233339A1 · Aug 11, 2016