Duty cycle detector and semiconductor integrated circuit apparatus including the same

1. A duty cycle detector, comprising:

a first storage unit;

a second storage unit;

a first enable unit configured to generate a first control signal in synchronization with a rising clock;

a second enable unit configured to generate a second control signal according to the first control signal and a falling clock;

a rising clock detection unit configured to change a voltage stored in the first storage unit according to the number of rising clocks to be detected during the enabling of the first control signal;

a falling clock detection unit configured to change a voltage stored in the second storage unit according to the number of falling clocks to be detected during the enabling of the second control signal; and

a comparison unit configured to compare the information of the first storage unit and the information of the second storage unit, changed by the rising clock detection unit and the falling clock detection unit, respectively, in response to a comparison enable signal.

2. The duty cycle detector according to claim 1 , wherein the comparison enable signal is activated after the first and second control signals.

3. The duty cycle detector according to claim 1 , further comprising:

a first precharge unit configured to precharge the first storage unit for a predetermined time, in response to a precharge signal; and

a second precharge unit configured to precharge the second storage unit for the predetermined time, in response to the precharge signal.

4. The duty cycle detector according to claim 1 ,

wherein the first enable unit comprises:

a divider configured to receive the rising clock and generate a divided clock;

a delay configured to receive the divided clock and generate a plurality of delayed clocks; and

a logic circuit configured to perform a logical operation on a part of the plurality of delayed clocks and generate the first control signal.

5. The duty cycle detector according to claim 4 ,

wherein the second enable unit receives the first control signal and an inverted signal of the falling clock, and outputs the second control signal.

6. A semiconductor integrated circuit apparatus comprising:

a duty cycle detector configured to generate a duty cycle detection signal;

a DLL circuit configured to detect a phase difference between a reference clock and a feedback clock and generate a DLL clock;

a duty cycle corrector configured to correct the duty cycle of the DLL clock in response to a duty cycle control signal, and output a corrected rising clock and a corrected falling clock; and

a duty cycle control signal generator configured to generate a duty cycle control signal in response to the duty cycle detection signal, during active periods of a rising strobe signal and a falling strobe signal,

wherein the duty cycle detector comprises:

a first storage unit;

a second storage unit;

a first enable unit configured to generate the rising strobe signal;

a second enable unit configured to generate the falling strobe signal;

a rising clock detection unit configured to change a voltage stored in the first storage unit according to the number of rising clocks to be detected during the enabling of the rising strobe signal;

a falling clock detection unit configured to change a voltage stored in the second storage unit according to the number of falling clocks to be detected during the enabling of the falling strobe signal; and

a comparison unit configured to compare the information of the first storage unit and the information of the second storage units changed by the rising clock detection unit and the falling clock detection unit, respectively, in response to a comparison enable signal.

7. The semiconductor integrated circuit apparatus according to claim 6 , wherein the comparison enable signal is activated after the rising strobe signal and the falling strobe signal.