IP Library › Granted Patent US 9,666,534
Granted Patent B2
US 9,666,534 · App. 14/276,398 · Granted May 30, 2017

Semiconductor interconnect structure and manufacturing method thereof

Inventor: Chih-Yuan Ting (Taipei, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
H01L23/53295H01L21/7682H01L21/76802H01L21/76816H01L21/76826H01L21/76832H01L21/76834H01L23/528H01L23/5222H01L23/5329H01L21/76852H01L2924/0002
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Quick Facts
Patent No.
US 9,666,534
App. No.
14/276,398
Granted
May 30, 2017
Kind
B2
Abstract

The present disclosure provides an interconnect structure, including a low k dielectric layer with an air gap region and a non-air gap region. A first conductive line is positioned in the air gap region, and a second conductive line is positioned in the non-air gap region of the low k dielectric layer. A height of the first conductive line is different from a height of the second conductive line. The present disclosure also provides a method for manufacturing a semiconductor interconnect structure, including forming a photoresist layer over a hard mask layer with openings exposing a low k dielectric layer; treating the low k dielectric layer to be more hydrophilic through the openings of the hard mask layer; and removing the treated low k dielectric region to form an air gap in the air gap region.

Claims (34)

1. An interconnect structure, comprising:

a low k dielectric layer over a substrate, comprising an air gap region having an air gap and a non-air gap region, the air gap further comprising a tapered sidewall and a bottom surface defined by the low k dielectric layer;

a first conductive line in the air gap region; and

a second conductive line in the non-air gap region,

wherein a major direction of the first conductive line and a major direction of the second conductive line are substantially perpendicular to the substrate, and a height of the first conductive line along the major direction thereof is different from a height of the second conductive line along the major direction thereof.

2. The interconnect structure of claim 1 , wherein a ratio of the height of the first conductive line and the height of the second conductive line is in a range of from about 0.8 to about 1.5.

3. The interconnect structure of claim 1 , wherein a separation between two adjacent first conductive lines is less than about 50 nm.

4. The interconnect structure of claim 1 , further comprising a cap layer over the air gap region of the low k dielectric layer.

5. The interconnect structure of claim 4 , further comprising a conformal layer composed of a single material being in direct contact with a top surface of the first conductive line and a top surface of the second conductive line.

6. The interconnect structure of claim 5 , wherein materials of the cap layer are substantially the same as materials of the conformal layer.

7. The interconnect structure of claim 6 , further comprising an internal low k material between two adjacent first conductive lines.

8. The interconnect structure of claim 7 , wherein a largest separation between a sidewall of the first conductive line and the internal low k material is below about 50 nm.

9. The interconnect structure of claim 5 , wherein the conformal layer comprising metal.

10. The interconnect structure of claim 1 ,

wherein a bottom portion of the first conductive line is surrounded by the low k dielectric layer and a top portion of the first conductive line is surrounded by an air gap of the air gap region.

11. The interconnect structure of claim 10 , further comprising:

a plurality of first conductive lines in the air gap region, a largest separation between two adjacent first conductive lines is less than about 50 nm.

12. The interconnect structure of claim 10 , further comprising:

a cap layer over the air gap region and the non-air gap region;

a third conductive line over the air gap region; and

a fourth conductive line over the non-air gap region.

13. The interconnect structure of claim 12 , wherein a width of the third conductive line is less than a width of the underlying first conductive line.

14. The interconnect structure of claim 12 , wherein the fourth conductive line is partially overlaid on the second conductive line.

15. A semiconductor interconnect structure, comprising:

a low k dielectric layer over a substrate;

an air gap in the low k dielectric layer, the air gap comprising a tapered sidewall and a substantially flat bottom surface defined by the low k dielectric layer;

a first conductive line in the low k dielectric layer, surrounded by the air gap; and

a second conductive line in the low k dielectric layer, surrounded by the low k dielectric layer;

wherein a bottom of the first conductive line is lower than a bottom of the second conductive line.

16. The semiconductor interconnect structure of claim 15 , further comprising a conformal barrier layer made of ceramics, metal oxynitride, dielectric film, or a combination thereof.

17. The semiconductor interconnect structure of claim 15 , further comprising a cap layer over the air gap, composed of ceramics, metal oxynitride, dielectric film, organic polymer films, or the combination thereof.

18. The semiconductor interconnect structure of claim 15 , wherein a difference between the bottom of the first conductive line and the bottom of the second conductive line is in a range of from about 10% to about 50% of a height of the first conductive line.

19. The semiconductor interconnect structure of claim 15 , wherein a width of the air gap between the first conductive line and the low k dielectric layer is less than about 50 nm.

20. The semiconductor interconnect structure of claim 15 , further comprising a conformal metal layer over a top surface and a sidewall of the first conductive line.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2014
From: TING, CHIH-YUAN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Reel/Frame 032880/0064 →
Continuity (1)
Related Publication 20150332999A1 · Nov 19, 2015