Oscillator circuit, corresponding apparatus and method
An oscillator has an oscillator output emitting an oscillating signal. The oscillator includes oscillator cores which each have a same circuit topology. A set of configuration switches couple a selected number of oscillator cores in parallel to generate the oscillating signal. The oscillator cores are arranged with a symmetry around a central axis. The planar inductors of the oscillator cores are arranged in a petal-like pattern with the planar inductors forming the petals of the petal-like pattern. The selected coupling of the oscillator cores in made in response to a selected phase noise threshold of a modulation device which receives the oscillating signal.
1. An oscillator, comprising:
a first oscillator core including a first bias input node and further including a first output node and a second output node with a first planar inductor coupled between the first and second output nodes of the first oscillator core;
a second oscillator core including a second bias input node and further including a third output node and a fourth output node with a second planar inductor coupled between the third and fourth output nodes of the second oscillator core;
a first switch coupled between the first output node and the third output node;
a second switch coupled between the second output node and the fourth output node;
a bias control circuit having a bias output node;
a third switch coupled between the bias output node and the first bias input node; and
a fourth switch coupled between the bias output node and the second bias input node;
wherein said first and second switches are selectively actuated to selectively connect the first and second oscillator cores in parallel to generate an output oscillation signal; and
wherein said third and fourth switches are selectively actuated to selectively enable oscillation operation of the first and second oscillator cores, respectively.
2. The oscillator of claim 1 , further comprising:
a third oscillator core including a third bias input node and further including a fifth output node and a sixth output node with a third planar inductor coupled between the fifth and sixth output nodes of the third oscillator core;
a fifth switch coupled between the first output node and the fifth output node;
a sixth switch coupled between the second output node and the sixth output node; and
a seventh switch coupled between the bias output node and the third bias input node;
wherein said first, second, fifth and sixth switches are selectively actuated to selectively connect the first, second and third oscillator cores in parallel to generate an output oscillation signal; and
wherein said third, fourth and seventh switches are selectively actuated to selectively enable oscillation operation of the first, second and third oscillator cores, respectively.
3. The oscillator of claim 2 , wherein said first, second and third oscillator cores have identical circuit layouts.
4. The oscillator of claim 2 , wherein said first, second and third oscillator cores are arranged symmetrically around a central axis.
5. The oscillator of claim 4 , wherein the symmetrical arrangement has a circular symmetry.
6. The oscillator of claim 4 , wherein the planar inductors of the first, second and third oscillator cores are arranged radially extending from the central axis.
7. The oscillator of claim 1 , further comprising:
a modulation device configured to receive said output oscillating signal, said modulation device operable with a plurality of phase noise thresholds, and
wherein said first through fourth switches are selectively actuated as a function of a phase noise threshold of said modulation device.