Duplexer-less transceiver and communication apparatus

1. A duplexer-less transceiver arrangement comprising:

a receiver arranged for frequency-division duplex communication with a communication network;

a transmitter arranged for frequency-division duplex communication with the communication network;

an antenna port for connecting to an antenna;

a balancing impedance circuit arranged to provide an adaptive impedance arranged to mimic the impedance at the antenna port; and

an impedance network comprising impedances and connections differentially connecting the antenna port to the receiver, differentially connecting the antenna port to the transmitter, differentially connecting the balancing impedance circuit to the receiver, and differentially connecting the balancing circuit to the transmitter, and wherein the impedance network cross-connects the transmitter to the antenna port and the balancing impedance circuit, and cross-connects the receiver to the antenna port and the balancing impedance circuit, to cancel or at least reduce transmitter-signal contribution at the receiver.

2. The transceiver according to claim 1 , wherein the impedances and connections of the impedance network are configured such that:

the antenna port is differentially connected to the receiver via a first pair of impedances, a second pair of impedances and a third pair of impedances, wherein one of each of the first pair of impedances, the second pair of impedances and the third pair of impedances are connected in series, and another of the first pair of impedances, the second pair of impedances and the third pair of impedances are connected in series;

the antenna port is differentially connected to the transmitter via the first pair of impedances, a fourth pair of impedances and a fifth pair of impedances, wherein one of each of the first pair of impedances, the fourth pair of impedances and the fifth pair of impedances are connected in series, and another of the first pair of impedances, the fourth pair of impedances and the fifth pair of impedances are connected in series;

the balancing impedance circuit is differentially connected to the receiver via a sixth pair of impedances, a seventh pair of impedances and the third pair of impedances, wherein one of each of the sixth pair of impedances and the seventh pair of impedances and the another of the third pair of impedances are connected in series, and another of the sixth pair of impedances and the seventh pair of impedances and the one of the third pair of impedances are connected in series;

the balancing impedance circuit is differentially connected to the transmitter via the sixth pair of impedances, an eighth pair of impedances and the fifth differential pair of impedances, wherein one of each of the sixth pair of impedances, the eighth pair of impedances and the fifth pair of impedances are connected in series, and another of the sixth differential pair of impedances, the eighth pair of impedances and the fifth pair of impedances are connected in series; and

the pairs of impedances are symmetrically arranged and symmetrically valued with respect to the differential connections such that transmitter signal contribution through the third differential pair of impedances and the receiver is reduced.

3. The transceiver arrangement according to claim 2 , wherein the impedances of the first, third, fifth and sixth pairs of impedances are inductances and the impedances of the second, fourth, seventh and eighth pairs of impedances are capacitances.

4. The transceiver arrangement according to claim 2 , wherein the impedances of the first, third, fifth and sixth pairs of impedances are capacitances and the impedances of the second, fourth, seventh and eighth pairs of impedances are inductances.

5. The transceiver arrangement according to claim 2 , wherein all of the impedances of the first, third, fifth and sixth pairs of impedances are implemented on-chip.

6. The transceiver arrangement according to claim 2 , wherein all of the impedances of the second, fourth, seventh and eighth pairs of impedances are implemented on-chip.

7. The transceiver arrangement according to claim 1 , further comprising a filter arrangement connected to differential outputs of the transmitter and/or at differential inputs of the receiver arranged to suppress transmitter output signal at frequency of reception.

8. The transceiver arrangement according to claim 7 , wherein the filter arrangement comprises a pair of filters where each respective filter of the pair is connected between a respective output of the differential output of the transmitter or input of the differential input of the receiver and a signal ground.

9. The transceiver arrangement according to claim 8 , wherein each respective filter of the pair is a frequency translated filter connected to the respective output of the differential output of the transmitter or input of the differential input of the receiver via a mixer clocked by any of the receiver frequency or the transmitter frequency.

10. The transceiver arrangement according to claim 9 , wherein the frequency translated filter is a low-pass filter arranged at the transmitter output, and the mixer is clocked by the transmitter frequency.

11. The transceiver arrangement according to claim 9 , wherein the frequency translated filter is a low-pass filter and is arranged at the receiver input, and the mixer is clocked by the receiver frequency.

12. The transceiver arrangement according to claim 7 , wherein the filter arrangement comprises a filter connected between differential outputs of the transmitter and/or between differential inputs of the receiver.

13. The transceiver arrangement according to claim 1 , further comprising a balun connected at the antenna port and arranged to convert the differential terminals of the antenna port to a single-ended port to an antenna.

14. The transceiver arrangement according to claim 13 , wherein the balun comprises a transformer, and at least a part of the first pair of impedances is formed by a winding of the transformer.

15. The transceiver arrangement according to claim 1 , further comprising amplitude and phase detectors at respective differential antenna port terminals and differential port terminals of the balancing impedance circuit, wherein the balancing impedance circuit comprises a controller arranged to control the adaptive impedance such that magnitude and phase are equal for the balancing impedance circuit to the antenna port.

16. A communication device configured for frequency division duplex communication via a communication network, said device comprising a duplexer-less transceiver arrangement according to claim 1 .