Response collector circuitry coupled with through silicon via and tap
The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.
1. An electrical device comprising:
(A) an integrated circuit die having functional circuitry and test circuitry, the die having through silicon input vias and through silicon output vias coupled to the functional circuitry and the test circuitry, the integrated circuit die having a first face and the through silicon vias having contact points on the first face; and
(B) a test interposer having a first face and a second face, the test interposer having through silicon input vias and through silicon output vias with contact points on the first and second faces, the contact points on the first face of the interposer being coupled with contact points on the first face of the integrated circuit die, the test interposer including:
(1) a first multiplexer having a first input coupled with the through silicon input vias of the test interposer, a control input, and an output coupled with the through silicon input vias of the integrated circuit die;
(2) a second multiplexer having a first input coupled with the through silicon input vias of the test interposer, a control input, and an output coupled with the through silicon input vias of the integrated circuit die;
(3) response collector circuitry having an input coupled with a through silicon via of the integrated circuit, a control input, and an output; and
(4) test access port circuitry having a test data input, a test clock input, a test mode select input, and a test data output, the test access port circuitry having control leads coupled to the first multiplexer, the second multiplexer, and the response collector, and an input coupled to the output of the response collector.
2. The device of claim 1 in which the test access port circuitry includes:
(A) a state machine having a clock input coupled with the test clock input, a mode input coupled with the test mode select input, and control outputs,
(B) an instruction register having a data input coupled with the test data input, a data output, and a control input coupled with a control output of the state machine,
(C) a data register having a data input coupled with the test data input, a data output, and a control input coupled with a control output of the state machine, and
(D) multiplexer circuitry having a first input coupled with the data output of the instruction register, a second input coupled with the data output of the data register, a control input coupled with a control output of the state machine, and a data output coupled with the test data output.
3. The device of claim 1 in which the contact points on the first face of the interposer are directly connected with the contact points on the first face of the integrated circuit die.
4. The device of claim 1 including another integrated circuit die between the first face of the integrated circuit die and the test interposer and in which the contact points on the first face of the test interposer are coupled with the contact points on the first face of the integrated circuit die through the another integrated circuit die.
5. The device of claim 1 including a substrate, the test interposer is mounted on the substrate, and the second face of the test interposer faces the substrate.
6. The device of claim 1 in which the test access port circuitry includes a state machine having a clock input coupled with the test clock input, a mode input coupled with the test mode select input, and control outputs, the state machine operating through states of Test Logic Reset, Run Test Idle, Select-DR And Select-IR.