IP Library › Granted Patent US 9,674,480
Granted Patent B2
US 9,674,480 · App. 14/871,727 · Granted Jun 6, 2017

Camera link recorder

Inventors: Katsuhito Chiba (Saitama-ken, JP); Ryotaro Hongo (Saitama-ken, JP); Hirotoshi Shimada (Tokyo, JP)
Assignee: TEAC Corporation
H04N5/77H04N9/8211H04N5/04
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Quick Facts
Patent No.
US 9,674,480
App. No.
14/871,727
Granted
Jun 6, 2017
Kind
B2
Abstract

There is provided a camera link recorder capable of recording sounds by a clock signal synchronized with a clock signal of a camera. A recorder is linked to a camera by means of an HDMI cable, and others. An HDMI receiver of the recorder reproduces an LRCK signal, which is an audio clock signal of a camera, from the HDMI signal, and outputs the LRCK signal. A CPU outputs a clock signal, which is generated from the LRCK signal when a frequency of the LRCK signal corresponds to a predetermined frequency of an audio CODEC, as a master clock signal to the audio CODEC. In other case, the clock signal generated from the internal clock signal CLK is output as a master clock signal to the audio CODEC.

Claims (12)

1. A camera link recorder comprising:

an HDMI receiver for receiving an audio clock signal of a camera according to an HDMI signal transmitted from the HDMI-linked camera;

a signal processing section for subjecting an input audio signal to digital conversion and encoding and storing the signal; and

a control section for supplying the audio clock signal as a master clock signal of the signal processing section when the audio clock signal generated by the HDMI receiver is at a predetermined frequency corresponding to the signal processing section, and for supplying an internal clock signal as the master clock signal of the signal processing section when there is not the audio clock signal or when the audio clock signal is not at a predetermined frequency corresponding to the signal processing section.

2. The camera link recorder according to claim 1 , further comprising:

a phase-locked loop circuit for matching a phase of the audio clock signal to a phase of the internal clock signal.

3. The camera link recorder according to claim 2 , wherein the audio clock signal is a signal generated from an LRCK signal.

4. The camera link recorder according to claim 1 , wherein the audio clock signal is an MCLK signal.

5. The camera link recorder according to claim 1 , further comprising:

a setting section for setting whether or not to establish synchronization with the audio clock signal of the camera, wherein the control section supplies the audio clock signal as the master clock signal when the setting section has already set synchronization, and supplies the internal clock signal as the master clock signal when the setting section has not set synchronization, thereby controlling power of the HDMI receiver to OFF.

6. The camera link recorder according to claim 1 , wherein the control section supplies the internal clock signal as the master clock signal when the HDMI cable is not linked, thereby controlling power of the HDMI receiver to an OFF position.

7. The camera link recorder according to claim 1 , wherein the control section selectively supplies either a signal generated from the LRCK signal or an MCLK signal as the master clock signal of the signal processing section by switching.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2015
From: CHIBA, KATSUHITO; HONGO, RYOTARO; SHIMADA, HIROTOSHI
To: TEAC CORPORATION
Reel/Frame 036698/0499 →
Priority Claims (3)
JP 2014-202900 · Oct 1, 2014 · national
JP 2015-146965 · Jul 24, 2015 · national
JP 2015-187989 · Sep 25, 2015 · national
Continuity (1)
Related Publication 20160100125A1 · Apr 7, 2016