IP Library › Granted Patent US 9,674,937
Granted Patent B2
US 9,674,937 · App. 15/001,557 · Granted Jun 6, 2017

Circuit board and method of manufacturing the same

Inventor: Jung-Hyun Park (Suwon-Si, KR)
Assignee: Samsung Electro-Mechanics Co., Ltd.
H05K1/0203H05K1/0298H05K1/115H05K3/42H05K3/4644
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Quick Facts
Patent No.
US 9,674,937
App. No.
15/001,557
Granted
Jun 6, 2017
Kind
B2
Abstract

A circuit board including a core layer having a first surface and a second surface opposite to the first surface; a first build-up layer and a second build-up layer formed on the first surface and the second surface of the core layer, respectively, and including a conductive pattern and a conductive via; and an outer layer formed on the surface of the first build-up layer and the second build-up layer, wherein at least one build-up layer of the first build-up layer and the second build-up layer comprises a photosensitive insulating layer in which a cavity is disposed and a thermal dissipation unit disposed in the cavity.

Claims (19)

1. A circuit board comprising:

a core layer comprising a first surface and a second surface opposite to the first surface;

a first build-up layer and a second build-up layer formed on the first surface and the second surface of the core layer, respectively, and comprising a conductive pattern and a conductive via; and

an outer layer formed on a surface of the first build-up layer or a surface of the second build-up layer,

wherein at least one build-up layer of the first build-up layer and the second build-up layer comprises a photosensitive insulating layer in which a cavity is disposed and a thermal dissipation unit is disposed in the cavity,

wherein the outer layer has a pad formed thereon, the pad being connected with an electronic component, and

wherein the pad is connected with the thermal dissipation unit through a heat dissipation via.

2. The circuit board of claim 1 , wherein a conductive material of the thermal dissipation unit is the same as a conductive material of a conductive via formed in the photosensitive insulating layer.

3. The circuit board of claim of claim 2 , wherein the conductive material comprises a metal seed layer formed on an inner surface of the cavity and a plating layer formed on the metal seed layer.

4. The circuit board of claim 1 , wherein the first build-up layer and the second build-up layer each comprises a plurality of build-up layers.

5. The circuit board of claim 4 , wherein the plurality of build-up layers of the first build-up layer, and the plurality of build-up layers of the second build-up layer and the core layer together comprises the heat dissipation via directly or indirectly connected to the thermal dissipation unit.

6. The circuit board of claim 4 , wherein at least one build-up layer among the first build-up layer and the second build-up layer comprises two or more build-up layers which are adjacent to each other and thermal dissipation units are formed in the two or more build-up layers which are adjacent to each other and are laminated to be overlapped in a laminated direction of the build-up layers.

7. The circuit board of claim 4 , wherein each of the first build-up layer and the second build-up layer comprises at least one build-up layer in which the thermal dissipation unit is formed.

8. The circuit board of claim 7 , wherein thermal dissipation units formed in the at least one build-up layer in each of the first build-up layer and the second buildup layer are laminated to be overlapped in a laminated direction of the build-up layer.

9. The circuit board of claim 7 , wherein the at least one build-up layer in each of the first build-up layer and the second build-up layer is formed in a different number of layers.

10. The circuit board of claim 1 wherein the thermal dissipation unit comprises a plurality of thermal dissipation units arranged asymmetrically with respect to the core layer.

11. The circuit board of claim 1 , wherein a conductor volume fraction of each of the first build-up layer and the second build-up layer are different from each other,

wherein the conductor volume fraction comprises a ratio of volume occupied by the conductive pattern and the conductive via, excluding the thermal dissipation unit, to the entire volume of the first build-up layer and the second build-up layer, and

wherein the thermal dissipation unit is arranged asymmetrically with respect to the core layer to reduce the difference of the conductor volume fractions of the first build-up layer and the second build-up layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 20, 2016
From: PARK, JUNG-HYUN
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 037532/0921 →
Priority Claims (1)
KR 10-2015-0090655 · Jun 25, 2015 · national
Continuity (1)
Related Publication 20160381781A1 · Dec 29, 2016