Apparatus for testing a package-on-package semiconductor device
An apparatus for testing a package-on-package semiconductor device includes a top cover, a lower base, a heat dissipation module, and a plurality of probes. The lower base is disposed under the top cover so as to form an internal accommodation space for receiving an upper chip. The heat dissipation module includes a heat sink arranged in the internal accommodation space and attached to an upper surface of the upper chip. The probes are arranged in the lower base so as to electrically connect the upper chip with a lower chip. By the heat sink arranged in the internal accommodation space formed of the top cover and the lower base, heat generated from the upper chip during operation of the upper chip can be greatly dissipated so that the performance and the service life of the upper chip can be improved.
1. An apparatus for testing a package-on-package semiconductor device, comprising:
a top cover;
a lower base arranged under the top cover, the top cover and the lower base forming an internal accommodation space for receiving an upper chip;
a heat dissipation module including a heat sink, which is arranged in the internal accommodation space and attached to an upper surface of the upper chip;
a plurality of probes arranged in the lower base for electrically connecting the upper chip with a lower chip; and
a suction nozzle;
wherein the heat dissipation module further includes a heat conduction block, the lower base includes a hollow portion, and the heat conduction block is arranged in the hollow portion between the upper chip and the lower chip; and
wherein the heat conduction block includes a bottom recess and a negative pressure passage, the suction nozzle is provided in the bottom recess, and the negative pressure passage is communicated with the suction nozzle and coupled to a negative pressure source.
2. The apparatus of claim 1 , wherein the plurality of probes are disposed in the lower base and distributed around the hollow portion, each of the plurality of probes penetrates the lower base and protrudes out of an upper surface and a lower surface of the lower base so as to be in electrical contact with the upper chip and with the lower chip.
3. The apparatus of claim 1 , wherein the lower base includes a negative pressure source channel, through which the negative pressure passage of the heat conduction block is communicated with the negative pressure source.
4. The apparatus of claim 3 , further including an O ring arranged at an interface between the negative pressure source channel of the lower base and the negative pressure passage of the heat dissipation block.
5. The apparatus of claim 1 , wherein the top cover includes an aperture, the heat sink includes a bottom plate portion and a fin portion vertically provided on the bottom plate portion, a lower surface of the heat sink is attached to the upper surface of the upper chip, and the fin portion is extended out of the aperture.
6. The apparatus of claim 5 , further including at least one spring, which is provided in the internal accommodation space between the top cover and the bottom plate portion of the heat sink.
7. An apparatus for testing a package-on-package semiconductor device, comprising:
an upper chip carrier for carrying an upper chip;
a heat dissipation module provided on the upper chip carrier, wherein the heat dissipation module includes a heat sink, which is in contact with an upper surface of the upper chip; and
a suction nozzle;
wherein the heat dissipation module further includes a heat conduction block which is arranged on a lower surface of the upper chip and in contact with an upper surface of a lower chip; and
wherein the heat conduction block includes a bottom recess and a negative pressure passage, the suction nozzle is provided in the bottom recess, and the negative pressure passage is communicated with the suction nozzle and coupled to a negative pressure source.