IP Library › Granted Patent US 9,679,520
Granted Patent B2
US 9,679,520 · App. 14/769,086 · Granted Jun 13, 2017

Array substrate, method of producing the same, and display apparatus

Inventors: Cuili Gai (Beijing, CN); Danna Song (Beijing, CN); Zhongyuan Wu (Beijing, CN)
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
G09G3/3266G09G3/20H01L23/50H01L27/3276G09G2300/0408G09G2300/0426G09G2300/08H01L2251/5315H01L2924/0002
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,679,520
App. No.
14/769,086
Granted
Jun 13, 2017
Kind
B2
Abstract

The present disclosure provides an array substrate, a method of producing the same and a display apparatus. The array substrate comprises: N rows of scan lines, N being a natural number; M columns of data lines, which are arranged to cross with the N rows of scan lines, M being a natural number; a display array comprising N×M pixel units defined by the N rows of scan lines and the M columns of data lines; and N columns of leading wires electrically connected to the N rows of scan lines respectively and led out in parallel to the M columns of data lines. It may narrow the frame of the display apparatus.

Claims (32)

1. An array substrate, comprising:

N rows of scan lines, N being a natural number;

M columns of data lines, which are arranged to cross with the N rows of scan lines, M being a natural number;

a display array, comprising N×M pixel units defined by the N rows of scan lines and the M columns of data lines; and

N columns of leading wires, electrically connected to the N rows of scan lines respectively and led out in parallel to the M columns of data lines,

wherein each column of the N columns of leading wires is located between two adjacent columns of data lines and there is a constant interval between each two columns of the N columns of leading wires; and

wherein:

the ┌N/2┐ th column or the └N/2┘ th column of the N columns of leading wires is located between two central columns of data lines in the M columns of data lines and electrically connected to a first row of the scan lines, and other leading wires on two sides of the ┌N/2┐ th column or the └N/2┘ th column of the N columns of leading wires are electrically connected to second through N th rows of the scan lines alternatively in sequence, respectively, wherein ┌N/2┐ represents a ceiling function that is equal to the mathematical result of N divided by 2 in a case that N is an even number and is equal to the first integer greater than the mathematical result of N divided by 2 in a case that N is an odd number, and └N/2┘ represents a floor function that is equal to the mathematical result of N divided by 2 in the case that N is an even number and is equal to the first integer smaller than the mathematical result of N divided by 2 in the case that N is an odd number; or

a first column of the N columns of leading wires is located between two columns of data lines on a first side of the M columns of data lines and electrically connected to a first row of the scan lines, and second through N th columns of the N columns of leading wires are connected to second through N th rows of the scan lines in sequence, respectively; or

an N th column of the N columns of leading wires is located between two columns of data lines on a second side of the M columns of data lines and electrically connected to the first row of the scan lines, and the (N−1) th through first columns of the N columns of leading wires are connected to the second to through N th rows of the scan lines in sequence, respectively.

2. The array substrate according to claim 1 , wherein contact holes are provided above the N rows of scan lines respectively and the N columns of leading wires are electrically connected to the N rows of scan lines via the contact holes, respectively.

3. The array substrate according to claim 1 , wherein the N columns of leading wires are made from a metal material.

4. The array substrate according to claim 1 , further comprising: a signal driving chip and a scan driving chip, wherein the signal driving chip is connected to the display array by the M columns of data lines and the scan driving chip is connected to the display array by the N columns of leading wires and the N rows of scan lines.

5. The array substrate according to claim 4 , wherein the signal driving chip and the scan driving chip are located on a same side of the display array.

6. A display apparatus comprising an array substrate according to claim 1 , the array substrate comprising:

N rows of scan lines, N being a natural number;

M columns of data lines, which are arranged to cross with the N rows of scan lines, M being a natural number;

a display array, comprising N×M pixel units defined by the N rows of scan lines and the M columns of data lines; and

N columns of leading wires, electrically connected to the N rows of scan lines respectively and led out in parallel to the M columns of data lines,

wherein the N columns of leading wires and the M columns of data lines are arranged in a common layer.

7. The display apparatus according to claim 6 , wherein the display apparatus is a top emitting type OLED display apparatus.

8. A method for producing an array substrate, comprising:

forming a first electrically conductive layer and patterning it to form N rows of scan lines, N being a natural number;

forming an insulation layer and forming N contact holes in the insulation layer, the N contact holes being located above the N rows of scan lines respectively; and

forming a second electrically conductive layer and patterning it to form M columns of data lines and N columns of leading wires arranged to cross with each other and to define N×M pixel units, the N columns of leading wires being led out from the N contact holes respectively, and in parallel to the M columns of data lines, wherein M is a natural number, wherein each column of the N columns of leading wires is located between two adjacent columns of data lines and there is a constant interval between each two columns of the N columns of leading wires;

wherein:

the ┌N/2┐ th column or the └N/2┘ th column of the N columns of leading wires is located between two central columns of data lines in the M columns of data lines and electrically connected to a first row of the scan lines, and other leading wires on two sides of the ┌N/2┐ th column or the └N/2┘ th column of the N columns of leading wires are electrically connected to second through N th rows of the scan lines alternatively in sequence, respectively, wherein ┌N/2┐ represents a ceiling function that is equal to the mathematical result of N divided by 2 in a case that N is an even number and is equal to the first integer greater than the mathematical result of N divided by 2 in a case that N is an odd number, and └N/2┘ represents a floor function that is equal to the mathematical result of N divided by 2 in the case that N is an even number and is equal to the first integer smaller than the mathematical result of N divided by 2 in the case that N is an odd number; or

a first column of the N columns of leading wires is located between two columns of data lines on a first side of the M columns of data lines and electrically connected to a first row of the scan lines, and second through N th columns of the N columns of leading wires are connected to second through N th rows of the scan lines in sequence, respectively; or

an N th column of the N columns of leading wires is located between two columns of data lines on a second side of the M columns of data lines and electrically connected to the first row of the scan lines, and the (N−1) th through first columns of the N columns of leading wires are connected to the second through N th rows of the scan lines in sequence, respectively.

9. The array substrate according to claim 2 , wherein the N columns of leading wires are made from a metal material.

10. The array substrate according to claim 2 , further comprising: a signal driving chip and a scan driving chip, wherein the signal driving chip is connected to the display array by the M columns of data lines and the scan driving chip is connected to the display array by the N columns of leading wires and the N rows of scan lines.

11. The array substrate according to claim 1 , wherein the N columns of leading wires and the M columns of data lines are arranged in a common layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2015
From: GAI, CUILI; SONG, DANNA; WU, ZHONGYUAN
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 036366/0162 →
Priority Claims (1)
CN 2014 1 0478775 · Sep 18, 2014 · national
Continuity (1)
Related Publication 20160253967A1 · Sep 1, 2016