IP Library › Granted Patent US 9,679,774
Granted Patent B2
US 9,679,774 · App. 14/217,913 · Granted Jun 13, 2017

Method for removing crystal originated particles from a crystalline silicon body

Inventors: Hans-Joachim Schulze (Taufkirchen, DE); Peter Irsigler (Obernberg/Inn, AT)
Assignee: Infineon Technologies AG
H01L21/2257H01L21/0257H01L21/02238H01L21/02524H01L21/02595H01L21/02636H01L21/2605H01L21/268H01L21/26513H01L21/30604H01L21/31105H01L21/324H01L21/3221H01L21/263H01L29/0623
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Quick Facts
Patent No.
US 9,679,774
App. No.
14/217,913
Granted
Jun 13, 2017
Kind
B2
Abstract

A method for removing crystal originated particles from a crystalline silicon body having opposite first and second surfaces includes increasing a surface area of at least one of the first and second surfaces. The method further includes oxidizing the increased surface area at a temperature of at least 1000° C. and for a duration of at least 20 minutes.

Claims (29)

1. A method for removing crystal originated particles from a crystalline silicon body having opposite first and second surfaces, the method comprising:

increasing a surface area of at least one of the first and second surfaces by forming a polysilicon layer on the at least one of the first and second surfaces of the crystalline silicon body, wherein a surface roughness of the polysilicon layer is greater than a surface roughness of the at least one of the first and second surfaces of the crystalline silicon body; and

oxidizing the increased surface area at a temperature of at least 1000° C. and for a duration of at least 20 minutes.

2. The method of claim 1 , wherein oxidizing the increased surface area comprises a moist oxidization process.

3. The method of claim 1 , wherein a duration of oxidizing the increased surface area is between 1 hour and 5 hours.

4. The method of claim 1 , wherein oxidizing the increased surface area is carried out in a temperature range between 1000° C. and 1300° C.

5. The method of claim 1 , further comprising removing at least part of the oxidized surface area.

6. The method of claim 5 , further comprising annealing the crystalline silicon body in a hydrogen containing atmosphere at temperatures greater than 800° C.

7. The method of claim 1 , wherein a thickness of the polysilicon layer is between 500 nm and 2 μm.

8. The method of claim 7 , further comprising doping at least part of the polysilicon layer with at least 10 17 cm −3 of phosphorus.

9. The method of claim 1 , wherein increasing the surface area of at least one of the first and second surfaces comprises locally etching the at least one of the first and second surfaces.

10. The method of claim 1 , further comprising etching a plurality of trenches into the crystalline silicon body.

11. The method of claim 10 , wherein a depth of the plurality of trenches is between 3 μm and 250 μm and a width of the plurality of trenches is between 1 μm and 30 μm.

12. The method of claim 10 , wherein a distance between neighboring ones of the plurality of trenches is between 1 μm and 30 μm.

13. The method of claim 10 , further comprising filling the plurality of trenches by lateral epitaxial growth.

14. The method of claim 13 , wherein the lateral epitaxial growth comprises in-situ doping.

15. The method of claim 13 , wherein doping the crystalline silicon body comprises proton irradiation through at least one of the first and second surfaces and a subsequent annealing process in a temperature range between 300° C. and 520° C.

16. The method of claim 13 , wherein doping the crystalline silicon body further comprises generating vacancies in the crystalline silicon body by electron irradiation.

17. The method of claim 13 , further comprising, after filling the trenches, forming a semiconductor layer on the crystalline silicon body at a side comprising at least part of the plurality of trenches filled by lateral epitaxial growth.

18. The method of claim 10 , further comprising forming the plurality of trenches at the first and second surfaces.

19. The method of claim 10 , wherein a ratio between a depth of the plurality of trenches and a thickness of the crystalline silicon body ranges between 0.5% and 100%.

20. The method of claim 10 , further comprising reducing an impurity concentration in the crystalline silicon body by a thermal process for diffusing at least part of the impurities out of the crystalline silicon body.

21. The method of claim 10 , further comprising introducing dopants through at least one of sidewalls and a bottom side of the plurality of trenches.

22. The method of claim 1 , wherein increasing the surface area of at least one of the first and second surfaces comprises forming a porous layer at at least one of the first and second surfaces.

23. The method of claim 1 , wherein increasing a surface area of the at least one of the first and second surfaces comprises irradiating the surface area with laser irradiation configured to melt an irradiated part of the crystalline silicon body.

24. The method of claim 1 , wherein increasing the surface area of the at least one of the first and second surfaces comprises a machining process and a subsequent surface cleaning process.

25. The method of claim 1 , wherein increasing the surface area of at least one of the first and second surfaces provides an increase of the surface area by at least 30%.

26. The method of claim 1 , wherein oxidizing the increased surface area is carried out at a temperature of at least 1100° C.

27. The method of claim 1 , further comprising forming a semiconductor layer on the crystalline semiconductor body.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2014
From: SCHULZE, HANS-JOACHIM; IRSIGLER, PETER
To: INFINEON TECHNOLOGIES AG
Reel/Frame 034029/0396 →
Continuity (1)
Related Publication 20150270130A1 · Sep 24, 2015