Solid-state imaging device and method of driving solid-state imaging device
A solid-state imaging device includes a pixel including a photoelectric conversion element, an accumulation unit accumulating charges generated by the photoelectric conversion element, a reset unit resetting the accumulation unit at a voltage of equal to or more than 4.05 V, and an amplifier transistor amplifying and outputting a signal corresponding to amount of accumulated charges, a vertical output line connected to the pixel, a current source circuit including first to third transistors flowing a constant current through the vertical output line, and a voltage setting circuit respectively setting the gate voltages of the first to third transistors to a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage and lower than the power supply voltage so as to set the drain-source voltage of each of the first to third transistors to equal to or less than 1.75 V.
1. A solid-state imaging device comprising:
a pixel including
a photoelectric conversion element,
an accumulation unit to which charges generated by the photoelectric conversion element are transferred,
a reset unit configured to reset the accumulation unit at a power supply voltage of equal to or more than 4.05 V, and
an amplifier transistor configured to amplify and output a signal corresponding to amount of charges accumulated in the accumulation unit;
a vertical output line which is connected to the pixel and to which the signal amplified by the amplifier transistor is output;
a current source circuit including a third transistor connected to the vertical output line, a second transistor connected in series with the third transistor, and a first transistor connected in series with the second transistor and configured to make a predetermined constant current flow through the vertical output line; and
a voltage setting circuit configured to set a gate voltage of the first transistor to a first voltage, a gate voltage of the second transistor to a second voltage higher than the first voltage, and a gate voltage of the third transistor to a third voltage higher than the second voltage and lower than the power supply voltage so as to set a drain-source voltage of each of the first transistor, the second transistor, and the third transistor to equal to or less than 1.75 V.
2. The solid-state imaging device according to claim 1 , wherein
the current source circuit further includes not less than one other transistor connected in series with the first transistor, the second transistor, and the third transistor.
3. The solid-state imaging device according to claim 1 , wherein
the voltage setting circuit is configured to set the first voltage and the second voltage so as to make the first transistor to make a predetermined constant current flow regardless of a voltage of the vertical output line.
4. The solid-state imaging device according to claim 3 , wherein
the current source circuit further includes not less than one other transistor connected in series with the first transistor, the second transistor, and the third transistor.
5. The solid-state imaging device according to claim 1 , wherein
the voltage setting circuit is configured to:
set the gate voltage of the third transistor to the third voltage when ISO sensitivity is a first set value, and
set the gate voltage of the third transistor to a fifth voltage higher than the third voltage when the ISO sensitivity is a second set value lower than the first set value.
6. The solid-state imaging device according to claim 5 , wherein
the current source circuit further includes not less than one other transistor connected in series with the first transistor, the second transistor, and the third transistor.
7. The solid-state imaging device according to claim 5 , wherein
the voltage setting circuit is configured to set the first voltage and the second voltage so as to make the first transistor to make a predetermined constant current flow regardless of a voltage of the vertical output line.
8. The solid-state imaging device according to claim 7 , wherein
the current source circuit further includes not less than one other transistor connected in series with the first transistor, the second transistor, and the third transistor.
9. The solid-state imaging device according to claim 1 , wherein
the voltage setting circuit is configured to set the gate voltage of the third transistor to a fourth voltage which turns off the third transistor during an unused period of the current source circuit.
10. The solid-state imaging device according to claim 9 , wherein
the current source circuit further includes not less than one other transistor connected in series with the first transistor, the second transistor, and the third transistor.
11. The solid-state imaging device according to claim 9 , wherein
the voltage setting circuit is configured to set the first voltage and the second voltage so as to make the first transistor to make a predetermined constant current flow regardless of a voltage of the vertical output line.
12. The solid-state imaging device according to claim 11 , wherein
the current source circuit further includes not less than one other transistor connected in series with the first transistor, the second transistor, and the third transistor.
13. The solid-state imaging device according to claim 9 , wherein
the voltage setting circuit is configured to:
set the gate voltage of the third transistor to the third voltage when ISO sensitivity is a first set value, and
set the gate voltage of the third transistor to a fifth voltage higher than the third voltage when the ISO sensitivity is a second set value lower than the first set value.
14. The solid-state imaging device according to claim 13 , wherein
the current source circuit further includes not less than one other transistor connected in series with the first transistor, the second transistor, and the third transistor.
15. The solid-state imaging device according to claim 13 , wherein
the voltage setting circuit is configured to set the first voltage and the second voltage so as to make the first transistor to make a predetermined constant current flow regardless of a voltage of the vertical output line.
16. The solid-state imaging device according to claim 15 , wherein
the current source circuit further includes not less than one other transistor connected in series with the first transistor, the second transistor, and the third transistor.
17. A solid-state imaging device comprising:
a pixel including
a photoelectric conversion element,
an accumulation unit to which charges generated by the photoelectric conversion element are transferred,
a reset unit configured to reset the accumulation unit at a power supply voltage, and
an amplifier transistor configured to amplify and output a signal corresponding to amount of charges accumulated in the accumulation unit;
a vertical output line which is connected to the pixel and to which the signal amplified by the amplifier transistor is output;
a current source circuit including a third transistor connected to the vertical output line, a second transistor connected in series with the third transistor, and a first transistor connected in series with the second transistor and configured to make a predetermined constant current flow through the vertical output line; and
a voltage setting circuit configured to set a gate voltage of the first transistor to a first voltage, a gate voltage of the second transistor to a second voltage higher than the first voltage, and a gate voltage of the third transistor to a third voltage higher than the second voltage and lower than the power supply voltage so as to prevent a drain-source voltage of each of the first transistor, the second transistor, and the third transistor from generating hot carriers.
18. A method of driving a solid-state imaging device including a pixel including a photoelectric conversion element, an accumulation unit to which charges generated by the photoelectric conversion element are transferred, a reset unit configured to reset the accumulation unit at a power supply voltage of equal to or more than 4.05 V, and an amplifier transistor configured to amplify and output a signal corresponding to amount of charges accumulated in the accumulation unit, a vertical output line to which the signal amplified by the amplifier transistor is output, and a current source circuit connected to the vertical output line, wherein the current source circuit includes a third transistor connected to the vertical output line, a second transistor connected in series with the third transistor, and a first transistor connected in series with the second transistor, the method comprising:
setting a gate voltage of the first transistor to a first voltage, a gate voltage of the second transistor to a second voltage higher than the first voltage, and a gate voltage of the third transistor to a third voltage higher than the second voltage and lower than the power supply voltage so as to set a drain-source voltage of each of the first transistor, the second transistor, and the third transistor to equal to or less than 1.75 V when reading out the signal from the pixel.
19. An imaging system comprising:
a solid-state imaging device; and
a signal processing unit configured to generate an image by using a signal output from the solid-state imaging device, wherein
the solid-state imaging device includes
a pixel including
a photoelectric conversion element,
an accumulation unit to which charges generated by the photoelectric conversion element are transferred,
a reset unit configured to reset the accumulation unit at a power supply voltage of equal to or more than 4.05 V, and
an amplifier transistor configured to amplify and output a signal corresponding to amount of charges accumulated in the accumulation unit,
a vertical output line which is connected to the pixel and to which the signal amplified by the amplifier transistor is output,
a current source circuit including a third transistor connected to the vertical output line, a second transistor connected in series with the third transistor, and a first transistor connected in series with the second transistor and configured to make a predetermined constant current flow through the vertical output line, and
a voltage setting circuit configured to set a gate voltage of the first transistor to a first voltage, a gate voltage of the second transistor to a second voltage higher than the first voltage, and a gate voltage of the third transistor to a third voltage higher than the second voltage and lower than the power supply voltage so as to set a drain-source voltage of each of the first transistor, the second transistor, and the third transistor to equal to or less than 1.75 V.
20. An imaging system comprising:
a solid-state imaging device; and
a signal processing unit configured to generate an image by using a signal output from the solid-state imaging device, wherein
the solid-state imaging device includes
a pixel including
a photoelectric conversion element, an accumulation unit to which charges generated by the photoelectric conversion element are transferred,
a reset unit configured to reset the accumulation unit at a power supply voltage, and
an amplifier transistor configured to amplify and output a signal corresponding to amount of charges accumulated in the accumulation unit;
a vertical output line which is connected to the pixel and to which the signal amplified by the amplifier transistor is output;
a current source circuit including a third transistor connected to the vertical output line, a second transistor connected in series with the third transistor, and a first transistor connected in series with the second transistor and configured to make a predetermined constant current flow through the vertical output line; and
a voltage setting circuit configured to set a gate voltage of the first transistor to a first voltage, a gate voltage of the second transistor to a second voltage higher than the first voltage, and a gate voltage of the third transistor to a third voltage higher than the second voltage and lower than the power supply voltage so as to prevent a drain-source voltage of each of the first transistor, the second transistor, and the third transistor from generating hot carriers.