Solid-state image sensor
An image sensor includes charge accumulation region of first conductivity type, floating diffusion of the first conductivity type, stacked semiconductor region having first region of second conductivity type arranged below the charge accumulation region, second region of the second conductivity type arranged above the first region, and third region of the second conductivity type arranged above the second region. The sensor further includes fourth region of the second conductivity type arranged in region between the charge accumulation region and the floating diffusion, below the floating diffusion, and above the stacked semiconductor region, transfer gate for transferring charges of the charge accumulation region to the floating diffusion, and fifth region of the second conductivity type arranged in region below the charge accumulation region and the fourth region, and above the stacked semiconductor region.
1. A solid-state image sensor comprising:
a charge accumulation region of a first conductivity type;
a floating diffusion of the first conductivity type;
a stacked semiconductor region which includes a first semiconductor region of a second conductivity type different from the first conductivity type arranged below the charge accumulation region, a second semiconductor region of the second conductivity type arranged above the first semiconductor region, and a third semiconductor region of the second conductivity type arranged above the second semiconductor region;
a fourth semiconductor region of the second conductivity type arranged in a region between the charge accumulation region and the floating diffusion, below the floating diffusion, and above the stacked semiconductor region;
a transfer gate configured to form a channel, in the fourth semiconductor region, for transferring charges of the charge accumulation region to the floating diffusion; and
a fifth semiconductor region of the second conductivity type arranged in a region below the charge accumulation region and the fourth semiconductor region, and above the stacked semiconductor region,
wherein with C1 being a peak value of an impurity concentration of the second conductivity type in the first semiconductor region, C2 being a peak value of an impurity concentration of the second conductivity type in the second semiconductor region, C3 being a peak value of an impurity concentration of the second conductivity type in the third semiconductor region, and C5 being a peak value of an impurity concentration of the second conductivity type in the fifth semiconductor region,
C2<C3<C1 and C5<C3
are satisfied.
2. The sensor according to claim 1 , wherein with C4 being a peak value of an impurity concentration of the second conductivity type in the fourth semiconductor region,
C5≧C4
is further satisfied.
3. The sensor according to claim 2 , wherein C3>C4 is further satisfied.
4. The sensor according to claim 2 , wherein C4<C1 is further satisfied.
5. The sensor according to claim 2 , wherein C3>C4, C4<C1, 3×C2≦C1, and C3/4≦C5 are further satisfied.
6. The sensor according to claim 1 , wherein 3×C2≦C1 is further satisfied.
7. The sensor according to claim 1 , wherein 5×C2≦C1 is further satisfied.
8. The sensor according to claim 1 , wherein C3/4≦C5 is further satisfied.
9. The sensor according to claim 1 , further comprising an element isolation portion arranged adjacent to the floating diffusion,
wherein the fifth semiconductor region includes a part arranged below the element isolation portion.
10. The sensor according to claim 9 , wherein the stacked semiconductor region includes the part arranged below the element isolation portion.
11. The sensor according to claim 1 , further comprising a semiconductor region of the second conductivity type arranged above the charge accumulation region.
12. The sensor according to claim 1 wherein 1×10 16 cm −3 ≦C1≦1×10 18 cm −3 , 1×10 15 cm −3 ≦C2≦5×10 16 cm −3 , 2×10 15 cm −3 ≦C3≦2×10 17 cm −3 , and 5×10 14 cm −3 ≦C5≦2×10 17 cm −3 are further satisfied.
13. A camera comprising:
a solid-state image sensor; and
a processor configured to process a signal output from the solid-state image sensor,
wherein the solid-state image sensor comprises:
a charge accumulation region of a first conductivity type;
a floating diffusion of the first conductivity type;
a stacked semiconductor region which includes a first semiconductor region of a second conductivity type different from the first conductivity type arranged below the charge accumulation region, a second semiconductor region of the second conductivity type arranged above the first semiconductor region, and a third semiconductor region of the second conductivity type arranged above the second semiconductor region;
a fourth semiconductor region of the second conductivity type arranged in a region between the charge accumulation region and the floating diffusion, below the floating diffusion, and above the stacked semiconductor region;
a transfer gate configured to form a channel, in the fourth semiconductor region, for transferring charges of the charge accumulation region to the floating diffusion in the fourth semiconductor region; and
a fifth semiconductor region of the second conductivity type arranged in a region below the charge accumulation region and the fourth semiconductor region, and above the stacked semiconductor region,
wherein with C1 being a peak value of an impurity concentration of the second conductivity type in the first semiconductor region, C2 being a peak value of an impurity concentration of the second conductivity type in the second semiconductor region, C3 being a peak value of an impurity concentration of the second conductivity type in the third semiconductor region, and C5 being a peak value of an impurity concentration of the second conductivity type in the fifth semiconductor region,
C2<C3<C1 and C5<C3
are satisfied.