Integrated circuit dies having alignment marks and methods of forming same
Dies having alignment marks and methods of forming the same are provided. A method includes forming a device on a substrate. A plurality of contact pads is formed over the substrate and the device. Simultaneously with forming the plurality of contact pads, one or more alignment marks are formed over the substrate and the device.
1. A method comprising:
forming a device on a substrate;
after forming the device, forming a plurality of contact pads over the substrate and the device; and
simultaneously with forming the plurality of contact pads, forming one or more alignment marks over the substrate and the device;
forming a passivation layer over the plurality of contact pads and the one or more alignment marks; and
patterning the passivation layer to form a plurality of openings in the passivation layer, wherein each of the plurality of openings exposes a first portion of a top surface of a respective one of the plurality of contact pads, and wherein a second portion of the top surface of the respective one of the plurality of contact pads remains unexposed after the patterning.
2. The method of claim 1 , further comprising:
dicing the substrate to form a die, the die having at least one alignment mark;
aligning, using the at least one alignment mark, the die to a workpiece; and
attaching the die to the workpiece.
3. The method of claim 2 , wherein the die is a discrete semiconductor device chip.
4. The method of claim 2 , wherein the workpiece comprises a plurality of encapsulated dies and one or more redistribution lines (RDLs) on plurality of encapsulated dies, the die being attached to the one or more RDLs, the one or more RDLs being interposed between the plurality of encapsulated dies and the die.
5. The method of claim 1 , wherein forming the plurality of contact pads and the one or more alignment marks comprises:
depositing a conductive layer over the substrate and the device; and
patterning the conductive layer to form the plurality of contact pads and the one or more alignment marks.
6. The method of claim 1 , further comprising forming connectors on the plurality of contact pads.
7. The method of claim 1 , wherein the one or more alignment marks are electrically isolated from the device.
8. A method comprising:
forming a device on a substrate;
forming one or more metallization layers over the substrate and the device;
after forming the one or more metallization layers, forming a conductive layer over the one or more metallization layers;
patterning the conductive layer to form a plurality of contact pads and one or more alignment marks, the one or more alignment marks being electrically isolated from the device; and
forming a patterned passivation layer over the plurality of contact pads and the one or more alignment marks, the patterned passivation layer covering entire top surfaces of the one or more alignment marks and portions of top surfaces of the plurality of contact pads.
9. The method of claim 8 , further comprising:
singulating the substrate to form a singulated die, the singulated die having at least one alignment mark;
aligning, using the at least one alignment mark, the singulated die to a workpiece; and
attaching the singulated die to the workpiece.
10. The method of claim 9 , wherein the workpiece comprises a plurality of encapsulated dies and one or more redistribution lines (RDLs) on plurality of encapsulated dies, the singulated die being attached to the one or more RDLs, the one or more RDLs being interposed between the singulated die and the plurality of encapsulated dies.
11. The method of claim 9 , wherein the singulated die is a discrete semiconductor device chip.
12. The method of claim 8 , further comprising forming connectors on the plurality of contact pads.
13. The method of claim 8 , wherein each of the one or more alignment marks has a polygonal shape as viewed from top.
14. A method comprising:
forming a device on a substrate;
depositing a dielectric layer over the substrate and the device;
depositing a conductive layer over the dielectric layer;
etching the conductive layer to form a plurality of contact pads and a plurality of alignment marks, the plurality of alignment marks being electrically isolated from the plurality of contact pads;
blanket depositing a passivation layer over the plurality of contact pads and the plurality of alignment marks; and
etching the passivation layer to form a plurality of openings in the passivation layer, wherein each of the plurality of openings exposes a first portion of a top surface of a respective one of the plurality of contact pads, and wherein at least a portion of the passivation layer contacts a second portion of the top surface of the respective one of the plurality of contact pads after the etching.
15. The method of claim 14 , further comprising forming a plurality of connectors over the plurality of contact pads, wherein each of the plurality of connectors extends through a respective one of the plurality of openings and physically contacts a respective one of the plurality of contact pads.
16. The method of claim 15 , further comprising:
singulating the substrate to form a singulated die, the singulated die having at least one alignment mark;
aligning, using the at least one alignment mark, the singulated die to a workpiece; and
attaching the singulated die to the workpiece.
17. The method of claim 16 , wherein the at least one alignment mark is located at a corner of the singulated die.
18. The method of claim 14 , wherein each of the plurality of alignment marks has a polygonal shape as viewed from top.
19. The method of claim 12 , wherein portions of the connectors laterally extend over the patterned passivation layer.
20. The method of claim 15 , wherein at least a portion of the passivation layer is interposed between each of the plurality of connectors and a respective one of the plurality of contact pads.