IP Library › Granted Patent US 9,685,433

Granted Patent B2

US 9,685,433 · App. 14/495,368 · Granted Jun 20, 2017

Capacitor device

Inventor: Chao-Chieh Li (Hsinchu, TW)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

H01L27/0629 H01L23/5223 H01L27/0805 H01L28/86 H01L29/93 H01L29/94 H01L2924/0002

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Quick Facts

Patent No.: US 9,685,433
App. No.: 14/495,368
Granted: Jun 20, 2017
Kind: B2

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USPTO Patent Center↗ Full Patent PDF↗

Abstract

In some embodiments, a capacitor device includes a metal-oxide-metal (MOM) capacitor array and a varactor array configured overlapping with the MOM capacitor array. The MOM capacitor array includes a first MOM capacitor unit. The first MOM capacitor unit includes a first electrode pattern and a second electrode pattern in a first metallization layer. The first electrode pattern includes a plurality of first fingers and a first bus interconnecting the plurality of first fingers. The second electrode pattern includes a plurality of second fingers and a second bus interconnecting the plurality of second fingers. The varactor array includes a first varactor unit. The first varactor unit includes a first electrode contacting region and a second electrode contacting region. The first electrode pattern contacts the first electrode contacting region. The second electrode pattern contacts the second electrode contacting region.

Claims (69)

1. A capacitor device, comprising:

a metal-oxide-metal (MOM) capacitor array comprising:

a first MOM capacitor unit comprising:

a first electrode pattern and a second electrode pattern in a first metallization layer, the first electrode pattern comprising a plurality of first fingers and a first bus interconnecting the plurality of first fingers, and the second electrode pattern comprising a plurality of second fingers and a second bus interconnecting the plurality of second fingers; and

a third electrode pattern and a fourth electrode pattern in a second metallization layer, the third electrode pattern comprising a plurality of third fingers and a third bus interconnecting the plurality of third fingers and the fourth electrode pattern comprising a plurality of fourth fingers and a fourth bus interconnecting the plurality of fourth fingers,

wherein

the third electrode pattern is stacked in a first staggered manner with the first electrode pattern such that at least some of the plurality of first fingers and the plurality of third fingers are partially overlapped, and first non-overlapped portions of the at least some of the plurality of first fingers and the plurality of third fingers extend along opposite sides of first overlapped portions of the at least some of the plurality of first fingers and the plurality of third fingers;

the third electrode pattern contacts the first electrode pattern;

the fourth electrode pattern is stacked in a second staggered manner with the second electrode pattern such that at least some of the plurality of second fingers and the plurality of fourth fingers are partially overlapped, and second non-overlapped portions of the at least some of the plurality of second fingers and the plurality of fourth fingers extend along opposite sides of second overlapped portions of the at least some of the plurality of second fingers and the plurality of fourth fingers; and

the fourth electrode pattern contacts the second electrode pattern.

2. The capacitor device according to claim 1 , wherein

the MOM capacitor array further comprises:

a second MOM capacitor unit comprising:

a fifth electrode pattern and a sixth electrode pattern in the first metallization layer, and a seventh electrode pattern and an eighth electrode pattern in the second metallization layer, the fifth electrode pattern comprising a plurality of fifth fingers and a fifth bus interconnecting the plurality of fifth fingers, the sixth electrode pattern comprising a plurality of sixth fingers and a sixth bus interconnecting the plurality of sixth fingers, the seventh electrode pattern comprising a plurality of seventh fingers and a seventh bus interconnecting the plurality of seventh fingers, the eighth electrode pattern comprising a plurality of eighth fingers and an eighth bus interconnecting the plurality of eighth fingers,

wherein

the seventh electrode pattern is stacked in the second staggered manner with the fifth electrode pattern such that at least some of the plurality of fifth fingers and the plurality of seventh fingers are partially overlapped, and third non-overlapped portions of the at least some of the plurality of fifth fingers and the plurality of seventh fingers extend along opposite sides of third overlapped portions of the at least some of the plurality of fifth fingers and the plurality of seventh fingers;

the eighth electrode pattern is stacked in the first staggered manner with the sixth electrode pattern such that at least some of the plurality of sixth fingers and the plurality of eighth fingers are partially overlapped, and fourth non-overlapped portions of the at least some of the plurality of sixth fingers and the plurality of eighth fingers extend along opposite sides of fourth overlapped portions of the at least some of the plurality of sixth fingers and the plurality of eighth fingers;

the first overlapped portions under the first staggered manner and the third overlapped portions under the second staggered manner have opposite overlapped sides of the plurality of first fingers and the plurality of third fingers, and overlapped sides of the plurality of the fifth fingers and the plurality of seventh fingers;

the second overlapped portions under the second staggered manner and the fourth overlapped portions under the first staggered manner have opposite overlapped sides of the plurality of second fingers and the plurality of fourth fingers, and overlapped sides of the plurality of sixth fingers and the plurality of eighth fingers; and

the second electrode pattern and the sixth electrode pattern are coupled together, and the third electrode pattern and the seventh electrode pattern are coupled together.

3. The capacitor device according to claim 2 , wherein

the second electrode pattern and the sixth electrode pattern are coupled together using the first metallization layer, and the third electrode pattern and the seventh electrode pattern are coupled together using the second metallization layer.

4. The capacitor device according to claim 1 , wherein

a first contacting finger in the plurality of first fingers in the first metallization layer contacts a third contacting finger in the plurality of third fingers in the second metallization layer or a second contacting finger in the plurality of second fingers in the first metallization layer contacts a fourth contacting finger in the plurality of fourth fingers in the second metallization layer;

at least one first non-contacting finger in the plurality of first fingers in the first metallization layer does not contact at least one third non-contacting finger in the plurality of third fingers in the second metallization layer or at least one second non-contacting finger in the plurality of second fingers in the first metallization layer does not contact at least one fourth non-contacting finger in the plurality of fourth fingers in the second metallization layer.

5. The capacitor device according to claim 4 , wherein

the first contacting finger and the second contacting finger are opposite borders of the plurality of first fingers and the plurality of second fingers, respectively.

6. The capacitor device according to claim 4 , wherein

the first contacting finger and the second contacting finger are adjacent borders of the plurality of first fingers and the plurality of second fingers, respectively.

7. The capacitor device according to claim 1 , wherein

the third electrode pattern is symmetrical to the first electrode pattern with respect to the first bus and the fourth electrode pattern is symmetrical to the second electrode pattern with respect to the second bus.

8. A capacitor device, comprising:

a MOM capacitor array comprising:

a first MOM capacitor unit comprising:

a first electrode pattern and a second electrode pattern in a first metallization layer, and a third electrode pattern and a fourth electrode pattern in a second metallization layer, the first electrode pattern comprising a plurality of first fingers and a first bus interconnecting the plurality of first fingers, the second electrode pattern comprising a plurality of second fingers and a second bus interconnecting the plurality of second fingers, the third electrode pattern comprising a plurality of third fingers and a third bus interconnecting the plurality of third fingers and the fourth electrode pattern comprising a plurality of fourth fingers and a fourth bus interconnecting the plurality of fourth fingers,

wherein

the third electrode pattern contacts the first electrode pattern; and

the fourth electrode pattern contacts the second electrode pattern;

a second MOM capacitor unit comprising:

wherein

the seventh electrode pattern contacts the fifth electrode pattern;

the eighth electrode pattern contacts the sixth electrode pattern; and

the second electrode pattern directly contacts the sixth electrode pattern using the first metallization layer, and the third electrode pattern directly contacts the seventh electrode pattern using the second metallization layer.

9. The capacitor device according to claim 8 , wherein

the first contacting finger and the second contacting finger are opposite borders of the plurality of first fingers and the plurality of second fingers, respectively.

10. The capacitor device according to claim 8 , wherein

the first contacting finger and the second contacting finger are adjacent borders of the plurality of first fingers and the plurality of second fingers, respectively.

11. A capacitor device, comprising:

a MOM capacitor array comprising:

a first MOM capacitor unit comprising:

wherein

12. The capacitor device according to claim 11 , wherein

13. The capacitor device according to claim 11 , wherein

the first contacting finger and the second contacting finger are opposite borders of the plurality of first fingers and the plurality of second fingers, respectively.

14. The capacitor device according to claim 11 , wherein

the first contacting finger and the second contacting finger are adjacent borders of the plurality of first fingers and the plurality of second fingers, respectively.

15. The capacitor device according to claim 8 , wherein

the second bus and the sixth bus are shared; and

the third bus and the seventh bus are shared.

16. The capacitor device according to claim 8 , wherein

the fifth electrode pattern is symmetrical to the first electrode pattern with respect to the first bus, the sixth electrode pattern is symmetrical to the second electrode pattern with respect to the second bus, the seventh electrode pattern is symmetrical to the third electrode pattern with respect to the third bus and the eighth electrode pattern is symmetrical to the fourth electrode pattern with respect to the fourth bus.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2014

From: LI, CHAO-CHIEH

To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Reel/Frame 033809/0343 →

Continuity (2)

Provisional Application 61882414 · Sep 25, 2013

Related Publication 20150084107A1 · Mar 26, 2015