Diode structures with controlled injection efficiency for fast switching
This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.
1. A semiconductor device disposed in a semiconductor substrate wherein:
the semiconductor substrate includes a first semiconductor layer of a first conductivity type disposed below a second semiconductor layer of a second conductivity type;
wherein said first semiconductor layer further comprises an injection efficiency controlling buffer layer of the first conductivity type immediately below said second semiconductor layer of the second conductivity type and a drift layer of the first conductivity type below the injection efficiency controlling buffer layer wherein the injection efficiency controlling buffer layer is more heavily doped than the drift region to control an injection efficiency of said second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer constituting a PiN (P-type/intrinsic/N-type) diode;
a vertical IGBT (insulate-gate bipolar transistor) is integrated with the PiN diode on the semiconductor substrate beside the PiN diode to form a reverse conducting IGBT wherein the vertical IGBT is disposed laterally side-by-side adjacent to the PiN diode on the semiconductor substrate having a metal layer covering over a top surface to function as an anode for the PiN diode and an emitter for the IGBT respectively; and
a doped region of a second-conductivity disposed below the first semiconductor layer to function as a collector electrode for the IGBT integrated with and disposed side-by-side adjacent to the PiN diode.
2. The semiconductor device according to claim 1 , further comprising:
a trench gate of the PiN diode extending from the metal layer into said injection efficiency controlling buffer layer to charge compensate the injection efficiency controlling buffer layer.
3. The semiconductor device according to claim 2 , wherein:
the trench gate further comprises a gate insulation layer surrounding the trench gate with a gate electrode filled in said trench gate and contacting the metal layer disposed on top of the trench gate.
4. The semiconductor device according to claim 2 , wherein:
the vertical IGBT further comprises a source region of the first conductivity type encompassed in the second semiconductor layer that constitutes an emitter/body region for the IGBT.
5. The semiconductor device according to claim 4 , wherein:
the IGBT further comprises a planar gate disposed on a top surface of the semiconductor substrate above the source region and the emitter/body region.
6. The semiconductor device according to claim 1 , wherein:
the IGBT further comprises a shield electrode disposed in a shield electrode trench surrounded by a trench insulation layer.
7. The semiconductor device according to claim 5 wherein:
the IGBT further comprises an extension region of the first conductivity type extending vertically in the emitter/body region from the first semiconductor layer to the planar gate.
8. The semiconductor device according to claim 6 , further comprising:
a metal layer disposed on a bottom surface of said semiconductor substrate to electrically connected to the collector electrode of the IGBT and also to function as a cathode electrode for the PiN diode.