Semiconductor device, manufacturing method thereof, and electronic device
A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).
1. A method for manufacturing a semiconductor device comprising the steps of:
forming a first insulating layer over a substrate;
forming a stack including a first metal oxide layer and a first oxide semiconductor layer over the first insulating layer;
etching the stack including the first metal oxide layer and the first oxide semiconductor layer into an island shape using a first mask to form a second metal oxide layer and a second oxide semiconductor layer;
forming a third metal oxide layer over the second oxide semiconductor layer and the first insulating layer;
forming a second insulating layer over the third metal oxide layer;
forming a third insulating layer by performing planarization treatment on the second insulating layer;
etching part of the third insulating layer using a second mask to form a fourth insulating layer with a groove portion that reaches the third metal oxide layer;
forming a fifth insulating layer over the fourth insulating layer and the third metal oxide layer;
forming a first conductive layer over the fifth insulating layer;
forming a gate electrode layer and a sixth insulating layer by performing planarization treatment on the first conductive layer and the fifth insulating layer until the fourth insulating layer is exposed;
etching the fourth insulating layer and the sixth insulating layer using the gate electrode layer as a mask to form a gate insulating layer; and
adding an ion to the second oxide semiconductor layer using the gate electrode layer as a mask to form a source region and a drain region.
2. A method for manufacturing a semiconductor device comprising the steps of:
forming a first insulating layer over a substrate;
forming a stack including a first metal oxide layer and a first oxide semiconductor layer over the first insulating layer;
etching the stack including the first metal oxide layer and the first oxide semiconductor layer into an island shape using a first mask to form a second metal oxide layer and a second oxide semiconductor layer;
forming a third metal oxide layer over the second oxide semiconductor layer and the first insulating layer;
forming a first gate insulating layer over the third metal oxide layer;
forming a second insulating layer over the first gate insulating layer;
forming a third insulating layer by performing planarization treatment on the second insulating layer;
etching part of the third insulating layer using a second mask to form a fourth insulating layer with a groove portion that reaches the first gate insulating layer;
forming a first conductive layer over the fourth insulating layer and the first gate insulating layer;
forming a gate electrode layer by performing planarization treatment on the first conductive layer until the fourth insulating layer is exposed;
etching the fourth insulating layer using the gate electrode layer as a mask to provide a region where the first gate insulating layer is exposed;
etching the first gate insulating layer using the gate electrode layer as a mask to form a second gate insulating layer; and
adding an ion to the second oxide semiconductor layer to form a source region and a drain region.
3. A method for manufacturing a semiconductor device comprising the steps of:
forming a first insulating layer over a substrate;
forming a stack including a first metal oxide layer and a first oxide semiconductor layer over the first insulating layer;
etching the stack including the first metal oxide layer and the first oxide semiconductor layer into an island shape using a first mask to form a second metal oxide layer and a second oxide semiconductor layer;
forming a third metal oxide layer over the second oxide semiconductor layer and the first insulating layer;
forming a first gate insulating layer over the third metal oxide layer;
forming a second insulating layer over the first gate insulating layer;
forming a third insulating layer by performing planarization treatment on the second insulating layer;
etching part of the third insulating layer using a second mask to form a fourth insulating layer with a groove portion that reaches the first gate insulating layer;
forming a fifth insulating layer over the fourth insulating layer and the first gate insulating layer;
forming a first conductive layer over the fifth insulating layer;
forming a gate electrode layer and a sixth insulating layer by performing planarization treatment on the first conductive layer and the fifth insulating layer until the fourth insulating layer is exposed;
etching the fourth insulating layer and the sixth insulating layer using the gate electrode layer as a mask to provide a region where the first gate insulating layer is exposed; and
adding an ion to the second oxide semiconductor layer to form a source region and a drain region.
4. The method for manufacturing a semiconductor device, according to claim 1 , wherein phosphorus, argon, or xenon is added as the ion.
5. The method for manufacturing a semiconductor device, according to claim 1 , wherein a dose of the ion added is greater than or equal to 1×10 14 ions/cm 2 and less than or equal to 5×10 16 ions/cm 2 .
6. A method for manufacturing a semiconductor device comprising the steps of:
forming a first insulating layer over a substrate;
forming a stack including a first metal oxide layer and a first oxide semiconductor layer over the first insulating layer;
etching the stack including the first metal oxide layer and the first oxide semiconductor layer into an island shape using a first mask to form a second metal oxide layer and a second oxide semiconductor layer;
forming a third metal oxide layer over the second oxide semiconductor layer and the first insulating layer;
forming a second insulating layer over the third metal oxide layer;
forming a third insulating layer by performing planarization treatment on the second insulating layer;
etching part of the third insulating layer using a second mask to form a fourth insulating layer with a groove portion that reaches the third metal oxide layer;
forming a fifth insulating layer over the fourth insulating layer and the third metal oxide layer;
forming a first conductive layer over the fifth insulating layer;
forming a gate electrode layer and a sixth insulating layer by performing planarization treatment on the first conductive layer and the fifth insulating layer until the fourth insulating layer is exposed;
etching the fourth insulating layer and the sixth insulating layer using the gate electrode layer as a mask to form a gate insulating layer including a region in contact with a side surface of the gate electrode layer and a seventh insulating layer including a region in contact with the gate insulating layer; and
adding an ion to the second oxide semiconductor layer to form a source region and a drain region.
7. The method for manufacturing a semiconductor device, according to claim 6 , wherein phosphorus, argon, or xenon is added as the ion.
8. The method for manufacturing a semiconductor device, according to claim 6 , wherein a dose of the ion added is greater than or equal to 1×10 14 ions/cm 2 and less than or equal to 5×10 16 ions/cm 2 .
9. The method for manufacturing a semiconductor device, according to claim 6 , wherein the semiconductor device comprises a region where an angle between a tangent of the side surface of the gate electrode layer and a bottom surface of the substrate is greater than or equal to 60° and less than or equal to 85°.