Digital imaging and pulse detection array
An imaging and pulse detection array includes: a plurality of pixels connected to a controller, the controller being configured to generate an image based on an image signal originating from each pixel in the plurality of pixels and configured to detect a pulse on at least one of the pixels in the plurality of pixels, and each of the pixels in the plurality of pixels including an imaging circuit and a pulse detection circuit, the imaging circuit and the pulse detection circuit including a shared circuit architecture, and wherein the imaging circuit and the pulse detection circuit include a shared portion.
1. An imaging and pulse detection array comprising:
a plurality of pixels connected to a controller, the controller being configured to generate an image based on an image signal originating from each pixel in said plurality of pixels and configured to detect a pulse on at least one of said pixels in said plurality of pixels;
each of said pixels in said plurality of pixels including an imaging circuit and a pulse detection circuit, the imaging circuit and the pulse detection circuit including a shared circuit architecture, and wherein said imaging circuit and said pulse detection circuit include a shared portion
the shared portion comprises an optical detection device configured to provide an optical detection input to each of said imaging circuit and said pulse detection circuit and a pulse detection output;
said pulse detection output being connected to a pulse processing circuit within each pixel of said plurality of pixels; and
said pulse processing circuit is a bandwidth-processing circuit including an AC-coupling and high pass filtering process, an asynchronous pulse generation process and a digital pulse detection process.
2. The imaging and pulse detection array of claim 1 , wherein said AC-coupling and high pass filtering process is a bandwidth processing process configured to remove frequencies below a pass threshold from the pulse detection output.
3. The imaging and pulse detection array of claim 1 , wherein said digital pulse detection process is a bandwidth processing process configured to identify a presence of a pulse on the pulse detection output.
4. The imaging and pulse detection array of claim 1 , wherein the asynchronous pulse generation process is a bandwidth processing process configured to reduce a number of pulse detection outputs passed to the controller by the pulse processing circuit.