Semiconductor device and formation thereof
View Patent ↗A semiconductor device and methods of formation are provided. The semiconductor device includes a gate over a channel portion of a fin. The fin includes a first active area of the fin having a first active area top surface coplanar with a first shallow trench isolation (STI) top surface of a first STI portion of STI, and a second active area of the fin having a second active area top surface coplanar with a second STI top surface of a second STI portion of the STI. The method herein negates a need to recess at least one of the fin, the first STI portion or the second STI portion during device formation. Negating a need to recess at least one of the fin, the first STI portion or the second STI portion enhances the semiconductor device formation and is more efficient than a semiconductor device formation that requires the recessing of at least one of a fin, a first STI portion or a second STI portion.
1. A method of forming a semiconductor device comprising:
forming a dielectric layer over a dummy gate, over a first active area of a fin and over a first shallow trench isolation (STI) portion surrounding the first active area, the dummy gate over a channel portion of the fin and over a gate portion of the STI surrounding the channel portion of the fin, where a first active area top surface of the first active area is coplanar with a first STI top surface of the first STI portion;
removing the dummy gate, such that a channel top surface of the channel portion of the fin is exposed and such that the gate portion of the STI is exposed;
removing the gate portion of the STI, such that channel sidewalls of the channel portion of the fin are exposed; and
forming a gate over the channel top surface and adjacent the channel sidewalls of the channel portion of the fin, such that the first active area top surface of the first active area remains coplanar with the first STI top surface of the first STI portion.
2. The method of claim 1 , comprising forming spacers adjacent the dummy gate, prior to the forming a dielectric layer.
3. The method of claim 1 , comprising:
forming a first layer over a substrate, the first layer having a first etch selectivity that is different than a substrate etch selectivity;
forming a second layer over the first layer, the second layer having a second etch selectivity that is substantially similar to the substrate etch selectivity; and
patterning the first layer and the second layer to form the fin.
4. The method of claim 1 , comprising performing chemical mechanical planarization (CMP) on the dielectric layer to expose a dummy gate top surface of the dummy gate, prior to the removing the dummy gate.
5. The method of claim 1 , the removing the dummy gate comprising etching.
6. The method of claim 1 , comprising forming a nitride layer over the dummy gate, over the first active area and over the first STI portion prior to the forming a dielectric layer.
7. The method of claim 1 , comprising removing a part of the first STI portion to expose first active area sidewalls of the first active area to form a first active area opening.
8. The method of claim 7 , forming at least one of an epitaxial (Epi) cap or a contact within the first active area opening.
9. A method of forming a semiconductor device comprising:
forming a dielectric layer over a dummy gate, over a first active area of a fin, over a second active area of the fin, over a first shallow trench isolation (STI) portion surrounding the first active area and over a second STI portion surrounding the second active area, the dummy gate over a channel portion of the fin and over a gate portion of the STI surrounding the channel portion of the fin, where a first active area top surface of the first active area is coplanar with a first STI top surface of the first STI portion and a second active area top surface of the second active area is coplanar with a second STI top surface of the second STI portion;
removing the dummy gate, such that a channel top surface of the channel portion of the fin is exposed and such that the gate portion of the STI is exposed;
removing the gate portion of the STI, such that channel sidewalls of the channel portion of the fin are exposed; and
forming a gate over the channel top surface and adjacent the channel sidewalls of the channel portion of the fin, such that the first active area top surface of the first active area remains coplanar with the first STI top surface of the first STI portion and the second active area top surface of the second active area remains coplanar with the second STI top surface of the second STI portion.
10. The method of claim 9 , comprising forming spacers adjacent the dummy gate, prior to the forming a dielectric layer.
11. The method of claim 9 , comprising performing chemical mechanical planarization (CMP) on the dielectric layer to expose a dummy gate top surface of the dummy gate, prior to the removing the dummy gate.
12. The method of claim 9 , comprising:
forming a first layer over a substrate, the first layer having a first etch selectivity that is different than a substrate etch selectivity;
forming a second layer over the first layer, the second layer having a second etch selectivity that is substantially similar to the substrate etch selectivity; and
patterning the first layer and the second layer to form the fin.
13. The method of claim 9 , comprising forming a nitride layer over the dummy gate, over the first active area, over the second active area, over the first STI portion and over the second STI portion prior to the forming a dielectric layer.
14. The method of claim 9 , comprising removing a part of the first STI portion to expose first active area sidewalls of the first active area to form a first active area opening and forming at least one of an epitaxial (Epi) cap or a contact within the first active area opening.
15. The method of claim 9 , comprising:
exposing a channel bottom surface of the channel portion of the fin; and
forming the gate under the channel bottom surface of the channel portion of the fin.
16. A method of forming a semiconductor device comprising:
defining a fin over a substrate;
forming a dielectric layer over the substrate, the dielectric layer in contact with a sidewall of the fin;
forming a dummy gate over the fin and over the dielectric layer, the dummy gate contacting a top surface of the fin and a top surface of the dielectric layer;
forming a spacer, the spacer in contact with the dummy gate;
forming a second dielectric layer over the dielectric layer after the forming a spacer, the second dielectric layer in contact with the top surface of the dielectric layer;
removing the dummy gate to expose a portion of the fin and a portion of the dielectric layer;
removing the portion of the dielectric layer to define an opening; and
forming a gate in the opening and over the portion of the fin.
17. The method of claim 16 , the gate comprising a gate dielectric in contact with a sidewall and a top surface of the portion of the fin.
18. The method of claim 16 , the removing the portion of the dielectric layer comprising exposing a portion of the substrate.
19. The method of claim 16 , the removing the dummy gate comprising exposing a sidewall of the spacer.
20. The method of claim 16 , comprising:
etching the second dielectric layer to expose a second portion of the fin; and
growing an epitaxial cap over the second portion of the fin.