Epitaxy in semiconductor structure and manufacturing method of the same
View Patent ↗The present disclosure provides a semiconductor structure having an insulating layer positioning on a substrate; a semiconductor fin partially located in the insulating layer; and a metal gate over the semiconductor fin and the insulating layer. The semiconductor fin includes a first region including a first lattice constant and a second region in proximity to the metal gate, including a second lattice constant. At least one dislocation is located only in the second region of the semiconductor fin. The present disclosure provides a method for manufacturing a semiconductor structure, including forming a gate over a first semiconductor layer, removing a portion of the first semiconductor layer in proximity to a sidewall of the gate and obtaining a recess, and forming a second semiconductor layer in the recess. At least one dislocation is in-situ formed in the second semiconductor layer without extending to the first semiconductor layer.
1. A method for manufacturing a semiconductor structure, comprising:
forming a gate over a first semiconductor layer having a first lattice constant;
removing a portion of the first semiconductor layer in proximity to a sidewall of the gate and obtaining a recess; and
forming a second semiconductor layer having a second lattice constant over the recess,
wherein at least one dislocation is in-situ formed in the second semiconductor layer without extending to the first semiconductor layer while applying an in-situ doping operation at the forming of the second semiconductor layer by vapor phase epitaxy, the at least one dislocation comprising a pinch off point spaced apart from an entire boundary between the first semiconductor layer and the second semiconductor layer.
2. The method for manufacturing a semiconductor structure of claim 1 , wherein the removing the portion of the first semiconductor layer comprises etching the first semiconductor layer by a wet etching, a dry etching, or the combination thereof to form the recess having a predetermined depth.
3. The method for manufacturing a semiconductor structure of claim 1 , wherein the forming the second semiconductor layer comprises performing a cyclic deposition etch operation, a selective epitaxial growth, or the combination thereof.
4. The method for manufacturing a semiconductor structure of claim 1 , wherein the forming the second semiconductor layer comprises forming phosphor-doped silicon carbide, pseudocubic Si 3 P 4 , or the combination thereof.
5. The method for manufacturing a semiconductor structure of claim 4 , wherein a ratio of a flow rate of a silicon precursor and a flow rate of a phosphor precursor is in a range of from about 0.2 to about 5.
6. A method for manufacturing a semiconductor structure, comprising:
forming a gate over a first semiconductor layer having a first lattice constant;
removing a portion of the first semiconductor layer in proximity to a sidewall of the gate and obtaining a recess; and
forming a second semiconductor layer having a second lattice constant over the recess,
wherein at least one dislocation is located only in the second semiconductor layer while applying an in-situ doping operation at the forming of the second semiconductor layer by vapor phase epitaxy, the at least one dislocation comprising a pinch off point spaced apart from an entire boundary of the first semiconductor layer and the second semiconductor layer.
7. The method for manufacturing a semiconductor structure of claim 6 , wherein the removing the portion of the first semiconductor layer comprises preserving a {001} plane at a bottom surface of the recess and a {111} plane at a slanted surface of the recess.
8. The method for manufacturing a semiconductor structure of claim 6 , wherein the forming the second semiconductor layer comprises forming a phosphorous-doped silicon carbide (SiC:P).
9. The method for manufacturing a semiconductor structure of claim 8 , wherein a ratio of a flow rate of a silicon precursor and a flow rate of a phosphor precursor is in a range of from about 0.2 to about 5.
10. The method for manufacturing a semiconductor structure of claim 8 , wherein a growth temperature of forming the second semiconductor layer is in a range of from about 600 to about 700 degrees Celsius, and a chamber pressure of forming the second semiconductor layer is in a range of from about 100 to about 600 Torr.
11. The method for manufacturing a semiconductor structure of claim 8 , wherein the forming the SiC:P comprises introducing monomethalsilane as carbon precursors with a flow rate of from about 100 to about 300 Standard-state Cubic Centimeters per Minute (SCCM).
12. A method for manufacturing a semiconductor structure, comprising:
forming a gate over a semiconductor fin having a first lattice constant;
removing a portion of the semiconductor fin in proximity to a sidewall of the gate and obtaining a recess; and
forming a regrowth layer having a second lattice constant over the recess by vapor phase epitaxy with an in-situ doping operation,
wherein an upright V-shaped dislocation is formed in the regrowth layer during the forming of the regrowth layer, the upright V-shaped dislocation being parallel to a longitudinal direction of the semiconductor fin.
13. The method for manufacturing a semiconductor structure of claim 12 , wherein the forming the regrowth layer comprises forming a source region or a drain region of the semiconductor structure.
14. The method for manufacturing a semiconductor structure of claim 12 , wherein the forming the regrowth layer comprises forming a pseudocubic Si 3 P 4 phase.
15. The method for manufacturing a semiconductor structure of claim 14 , wherein a ratio of a flow rate of a silicon precursor and a flow rate of a phosphor precursor is in a range of from about 0.2 to about 5.
16. The method for manufacturing a semiconductor structure of claim 14 , wherein a growth temperature of the forming of the regrowth layer is in a range of from about 600 to about 700 degrees Celsius, and a chamber pressure of the forming of the regrowth layer is in a range of from about 100 to about 600 Torr.
17. The method for manufacturing a semiconductor structure of claim 12 , wherein the forming the regrowth layer comprises forming a phosphorous-doped silicon carbide (SiC:P).
18. The method for manufacturing a semiconductor structure of claim 12 , wherein the forming the gate over the semiconductor fin comprises forming a polysilicon gate over the semiconductor fin of a FinFET.