IP Library Granted Patent US 9,703,612
Granted Patent B2
US 9,703,612 · App. 13/438,205 · Granted Jul 11, 2017

Virtual architecture generating apparatus and method, and runtime system, multi-core system and methods of operating runtime system and multi-core system

Inventors: Min Young Son (Yongin-si, KR); Shi Hwa Lee (Seoul, KR); Seung Won Lee (Hwaseong-si, KR); Jeong Joon Yoo (Hwaseong-si, KR); Jae Don Lee (Paju-si, KR); Young Sam Shin (Hwaseong-si, KR); Hee Jin Ahn (Seoul, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
G06F9/5088G06F8/447G06F9/45558G06F11/3466G06F2009/4557
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Quick Facts
Patent No.
US 9,703,612
App. No.
13/438,205
Granted
Jul 11, 2017
Kind
B2
Abstract

A virtual architecture generating apparatus and method, a runtime system, a multi-core system, and methods of operating the runtime system and the multi-core system may include analyzing a requirement of an application, a feature of the application, and a requirement of a system enabling an execution of the application, and include generating a virtual architecture corresponding to the application, based on a physical architecture of a reconfigurable processor, the analyzed requirements and the analyzed feature.

Claims (20)

1. A method of operating a runtime system to tune an execution performance based on a virtual architecture, the method comprising:

generating, by a processor, a plurality of virtual architectures of a reconfigurable processor so that the virtual architectures correspond to an application;

generating a plurality of binary files associated with the application, based on the generated virtual architectures;

executing a part of each of the binary files in a virtual architecture corresponding to each of the binary files, and recording an execution performance of each of the binary files; and

selecting a binary file with a highest execution performance from among the binary files, and executing the other part of the selected binary file in a virtual architecture corresponding to the selected binary file,

wherein the generating of the virtual architectures corresponding to the application is based on a subset of a physical architecture of the reconfigurable processor.

2. The method of claim 1 , wherein the generating of the virtual architectures comprises:

analyzing a requirement of the application, and a requirement of a system, the system enabling an execution of the application;

analyzing a feature of the application; and

generating the virtual architectures corresponding to the application, based on the analyzed requirements, and the analyzed feature.

3. A non-transitory computer readable recording medium storing a program to cause a computer to implement the method of claim 1 .

4. A runtime system for tuning an execution performance based on a virtual architecture, the runtime system comprising:

a generating unit to generate a plurality of virtual architectures of a reconfigurable processor so that the virtual architectures correspond to an application;

a compiling unit to generate a plurality of binary files associated with the application, based on the generated virtual architectures; and

a processing unit to execute a part of each of the binary files in a virtual architecture corresponding to each of the binary files, to record an execution performance of each of the binary files, to select a binary file with a highest execution performance from among the binary files, and to execute the other part of the selected binary file in a virtual architecture corresponding to the selected binary file,

wherein the generating unit is configured to generate the virtual architectures corresponding to the application based on a subset of a physical architecture of the reconfigurable processor.

5. The runtime system of claim 4 , wherein the generating unit is configured:

to analyze a requirement of the application, and a requirement of a system, the system enabling an execution of the application;

to analyze a feature of the application; and

to generate the virtual architectures corresponding to the application, based on the analyzed requirements and the analyzed feature.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2012
From: SON, MIN YOUNG; LEE, SHI HWA; LEE, SEUNG WON; YOO, JEONG JOON; LEE, JAE DON; SHIN, YOUNG SAM; AHN, HEE JIN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 028147/0624 →
Priority Claims (1)
KR 10-2011-0110465 · Oct 27, 2011 · national
Continuity (1)
Related Publication 20130111472A1 · May 2, 2013