Approach to correct ECC errors using duplicate copies of data

1. A method comprising:

receiving a write command with a set of data that is temporarily stored at a first memory page, wherein a copy of the set of data is temporarily stored at a second memory page;

reading, from the first memory page, the set of data;

in response to determining that a number of bits in error in the set of data exceed a threshold for an error correction code (ECC) engine, reading, from the second memory page, the copy of the set of data;

in response to determining that a number of bits in error in the copy of the set of data exceed the threshold for the ECC engine, comparing the set of data with the copy of the set of data;

modifying the ECC engine based on the comparison;

processing the set of data and the copy of the set of data using the modified ECC engine to correct errors; and

storing the data permanently, based on the comparison after the errors are corrected.

2. The method of claim 1 wherein determining that the number of bits in error in the set of data exceeds the threshold is based on processing the set of data with the ECC engine.

3. The method of claim 1 wherein determining that the number of bits in error in the copy of the set of data exceeds the threshold is based on processing the copy of the set of data with the ECC engine.

4. The method of claim 1 wherein using the data and the copy of the data to modify the ECC engine comprises performing an exclusive or (XOR) operation between the data and the copy of the data.

5. The method of claim 4 further comprising locating a respective location of non-zero bits in a result of the XOR operation and modifying the ECC engine based on the respective locations.

6. The method of claim 1 further comprises storing a reference to the first memory page in a first entry of a data structure and a reference to the second memory page in a second entry of the data structure.

7. The method of claim 6 further comprises storing an indication in the data structure in response to detecting that the number of bits in error in the set of data and in the copy of the set of data exceeds the threshold.

8. A device comprising:

a first and second memory page, each storing a copy of a set of data;

a logic unit configured to perform logic operations on data stored in the first and second memory page;

an error correction code (ECC) engine modification unit configured to modify parameters of an ECC engine; and

an enhanced post write read (EPWR) unit configured to:

determine that a number of bits in error in the data read from the first memory page and the secondary page exceeds a threshold of the ECC engine;

cause the logic unit to compare data read from the first memory page with data read from the second memory page; and

cause the ECC engine modification unit to configure the ECC engine based on a result of the comparison.

9. The device of claim 8 wherein the logic unit in response to being caused to compare data read from the first memory page with data read from the second memory page is configured to perform a bitwise exclusive or (XOR) operation between data read from the first memory page and data read from the second memory page.

10. The device of claim 8 wherein the ECC engine implements the low-density parity-check code (LDPC) and wherein the parameter modified by the ECC engine modification unit corresponds to an error probability of the ECC engine.

11. A storage device comprising:

a memory comprising memory blocks for data storage;

a controller coupled with the memory for programming the memory blocks;

an error correction code (ECC) engine coupled with the controller configured to correct errors in data when a number of errors is below a threshold for a first copy of the data from dual programming and without reading from a second copy of the data; and

an enhanced post write read (EPWR) unit configured to compare the first copy of the data with the second copy of the data when the number of errors is above the threshold for the second copy of the data in addition to the first copy of the data.

12. The storage device of claim 11 , wherein the dual programming comprises programming of the memory blocks with a first copy and a second copy of data for error correction purposes.

13. The storage device of claim 12 , wherein the first copy and the second copy are duplicate copies of data stored in update blocks.

14. The storage device of claim 13 , wherein the data is committed from only one of the first copy or the second copy.

15. The storage device of claim 14 , wherein the first copy comprises a primary block from the memory blocks and the second copy comprises a secondary block from the memory blocks.

16. The storage device of claim 15 , wherein the data is committed from the secondary block only when the primary block includes uncorrectable ECC (UECC) errors.

17. The storage device of claim 16 , wherein the UECC error includes when the number of errors is above the threshold.

18. The storage device of claim 17 , wherein when the number of errors is above the threshold for both the primary block and the secondary block, the EPWR unit is configured to compare the data stored in the primary block with the data stored in the secondary block.

19. The storage device of claim 11 , wherein the ECC engine is updated based on the comparison to increase error probabilities associated with a location of set bits and decrease error probabilities associated with a location of zero bits.

20. The storage device of claim 11 , wherein errors from both copies of data are corrected based on the comparison.