Sense amplifier with offset compensation
An amplifier circuit is disclosed having an amplifier with first and second input terminals coupled to receive an input signal. A first compensation circuit is coupled to the first input terminal, and a second compensation circuit is coupled to the second input terminal. A programmable latch circuit is arranged to select one of the first and second compensation circuits.
1. An amplifier circuit, comprising:
an amplifier having first and second input terminals;
a first compensation circuit coupled to the first input terminal;
a second compensation circuit coupled to the second input terminal; and
a programmable latch circuit arranged to select one of the first and second compensation circuits, such that when the first compensation circuit is selected, the second compensation circuit is not selected, and when the second compensation circuit is selected, the first compensation circuit is not selected.
2. The amplifier circuit of claim 1 , wherein the first compensation circuit comprises a first capacitor connected in series with a first transistor, and wherein the second compensation circuit comprises a second capacitor connected in series with a second transistor.
3. The amplifier circuit of claim 1 , wherein the first compensation circuit comprises a plurality of capacitors having a substantially same value, and wherein the second compensation circuit comprises a plurality of capacitors having the substantially same value.
4. The amplifier circuit of claim 1 , wherein the first compensation circuit comprises a plurality of capacitors having binary weighted values, and wherein the second compensation circuit comprises a plurality of capacitors having the binary weighted values.
5. The amplifier circuit of claim 1 , wherein the programmable latch circuit comprises a plurality of electronic fuse latch circuits.
6. The amplifier circuit of claim 1 , wherein the programmable latch circuit comprises a plurality of electronic antifuse latch circuits.
7. The amplifier circuit of claim 1 , wherein the programmable latch circuit comprises a plurality of latch circuits coupled to receive data from a nonvolatile memory array.
8. The amplifier circuit of claim 1 , comprising a sense amplifier circuit of a memory array.
9. The amplifier circuit of claim 1 , comprising a column of memory cells having a normal array of memory cells and a reserved array of memory cells.
10. A system, comprising:
a processor circuit;
an input device coupled to the processor circuit;
an output device coupled to the processor circuit;
a memory array coupled to the processor circuit; and
a sense amplifier of the memory array, comprising;
a first compensation circuit coupled to a first input terminal of the sense amplifier;
a second compensation circuit coupled to a second input terminal of the sense amplifier; and
a programmable latch circuit arranged to select one of the first and second compensation circuits, such that when the first compensation circuit is selected, the second compensation circuit is not selected, and when the second compensation circuit is selected, the first compensation circuit is not selected.
11. The system of claim 10 , wherein the first compensation circuit comprises a first capacitor connected in series with a first transistor, and wherein the second compensation circuit comprises a second capacitor connected in series with a second transistor.
12. The system of claim 10 , wherein the programmable latch circuit comprises a plurality of electronic fuse latch circuits.
13. The system of claim 10 , wherein the programmable latch circuit comprises a plurality of latch circuits coupled to receive data from a nonvolatile memory array.
14. The system of claim 10 , comprising a column of memory cells having a normal array of memory cells and a reserved array of memory cells coupled to the sense amplifier.
15. A circuit, comprising:
a memory array having a plurality of memory cells connected to first and second bit lines;
a sense amplifier having a first input terminal coupled to the first bit line and having a second input terminal coupled to the second bit line;
a first compensation circuit coupled to the first input terminal;
a second compensation circuit coupled to the second input terminal; and
a programmable latch circuit arranged to select one of the first and second compensation circuits, such that when the first compensation circuit is selected, the second compensation circuit is not selected, and when the second compensation circuit is selected, the first compensation circuit is not selected.
16. The circuit of claim 15 , wherein the first compensation circuit comprises a first capacitor connected in series with a first transistor, and wherein the second compensation circuit comprises a second capacitor connected in series with a second transistor.
17. The circuit of claim 15 , wherein the first compensation circuit comprises a plurality of capacitors having a substantially same value, and wherein the second compensation circuit comprises a plurality of capacitors having the substantially same value.
18. The circuit of claim 15 , wherein the first compensation circuit comprises a plurality of capacitors having binary weighted values, and wherein the second compensation circuit comprises a plurality of capacitors having the binary weighted values.
19. The circuit of claim 15 , wherein the programmable latch circuit comprises a plurality of electronic fuse latch circuits.
20. The circuit of claim 15 , wherein the programmable latch circuit comprises a plurality of latch circuits coupled to receive data from a nonvolatile memory array.