Chip on package structure and method
A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.
1. A semiconductor device comprising:
a first semiconductor die connected to a second semiconductor die, the second semiconductor die comprising a plurality of through silicon vias;
a third semiconductor die laterally removed from the second semiconductor die, wherein the third semiconductor die is electrically connected to the first semiconductor die through the plurality of through silicon vias and wherein the third semiconductor die does not have a through silicon via;
an encapsulant encapsulating the second semiconductor die and the third semiconductor die; and
vias extending all of the way through the encapsulant.
2. The semiconductor device of claim 1 , wherein the second semiconductor die is a 28 nm node device and the third semiconductor die is a 16 nm node device.
3. The semiconductor device of claim 1 , wherein the first semiconductor die is a memory device with a data transfer rate of between about 0.2 Gb/s and about 3.2 Gb/s.
4. The semiconductor device of claim 3 , wherein the first semiconductor die is a cache memory for the third semiconductor die.
5. The semiconductor device of claim 3 , a fourth semiconductor die located over the third semiconductor die, wherein the fourth semiconductor die comprises a memory with a data transfer rate less than the first semiconductor die.
6. The semiconductor device of claim 5 , wherein the fourth semiconductor die has a bandwidth of between about 6.4 GB/s and about 25.6 GB/s.
7. The semiconductor device of claim 5 , wherein the fourth semiconductor die has a larger capacity than the first semiconductor die.
8. A semiconductor device comprising:
a first redistribution layer;
a first semiconductor device, wherein the first semiconductor device has a first surface facing away from the first redistribution layer, the first surface being free from external connections;
a second semiconductor device separated from the first semiconductor device by an encapsulant, wherein the second semiconductor device has a second surface facing away from the first redistribution layer, the second surface comprising first external connections;
a third semiconductor device located over the second semiconductor device, wherein the first semiconductor device is electrically connected to the third semiconductor device through the first redistribution layer and the first external connections; and
through silicon vias extending from a first side of the encapsulant to a second side of the encapsulant.
9. The semiconductor device of claim 8 , wherein the first semiconductor device has a first operating speed, the second semiconductor device has a second operating speed, and the first operating speed is larger than the second operating speed.
10. The semiconductor device of claim 8 , wherein the third semiconductor device is an LPDDRn memory device.
11. The semiconductor device of claim 10 , further comprising a fourth semiconductor device electrically connected to the through silicon vias.
12. The semiconductor device of claim 11 , wherein the fourth semiconductor device is an LPDDR memory device.
13. The semiconductor device of claim 8 , further comprising:
a fourth semiconductor device electrically connected to the through silicon vias; and
a fifth semiconductor device physically connected to the fourth semiconductor device and electrically connected to the through silicon vias.
14. The semiconductor device of claim 13 , wherein both of the fourth semiconductor device and the fifth semiconductor device have a capacity larger than the third semiconductor device.
15. A semiconductor device comprising:
a first package with a first set of external connections; and
a second package electrically connected to the first package through the first set of external connections, the second package comprising:
an encapsulant with a first side and a second side opposite the first side;
through vias extending from the first side to the second side;
a first semiconductor device embedded within the encapsulant and separated from the through vias;
a second semiconductor device embedded within the encapsulant and separated from the through vias and the first semiconductor device; and
a third semiconductor device located outside of the encapsulant and electrically connected to the first semiconductor device by through silicon vias, the through silicon vias being located within the second semiconductor device.
16. The semiconductor device of claim 15 , wherein the second semiconductor device has a hybrid configuration.
17. The semiconductor device of claim 16 , wherein the hybrid configuration comprises an analog region and a digital region.
18. The semiconductor device of claim 15 , wherein the first package further comprises a fourth semiconductor device, the fourth semiconductor device having a first bandwidth.
19. The semiconductor device of claim 18 , wherein the third semiconductor device has a second bandwidth greater than the first bandwidth.
20. The semiconductor device of claim 19 , wherein the second bandwidth is about 51.2 GB/s and the first bandwidth is between about 6.4 GB/s and about 25.6 GB/s.