Semiconductor devices
Provided is a semiconductor device, including gate structures on a substrate, the gate structures extending parallel to a first direction and being spaced apart from each other by a separation trench interposed therebetween, each of the gate structures including insulating patterns stacked on the substrate and a gate electrode interposed therebetween; vertical pillars connected to the substrate through the gate structures; an insulating spacer in the separation trench covering a sidewall of each of the gate structures; and a diffusion barrier structure between the gate electrode and the insulating spacer.
1. A semiconductor device, comprising:
gate structures on a substrate, the gate structures extending parallel to a first direction and being spaced apart from each other by a separation trench interposed therebetween, each of the gate structures including insulating patterns stacked on the substrate and a gate electrode interposed therebetween;
vertical pillars connected to the substrate through the gate structures;
an insulating spacer in the separation trench covering a sidewall of each of the gate structures; and
a diffusion barrier structure between the gate electrode and the insulating spacer, wherein the diffusion barrier structure includes an air gap between the gate electrode and the insulating spacer.
2. The device as claimed in claim 1 , further comprising:
a common source region in a portion of the substrate located below the separation trench; and
a strapping plug in the separation trench extending from the common source region to a top level of the gate structures, wherein the insulating spacer is between the sidewalls of the gate structures and the strapping plug.
3. The device as claimed in claim 2 , wherein the strapping plug is a bar-shaped structure extending in the first direction, when viewed in a plan view.
4. The device as claimed in claim 2 , wherein the strapping plug includes a metal nitride layer and a tungsten layer on the metal nitride layer.
5. The device as claimed in claim 1 , wherein the insulating spacer includes a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, and/or an aluminum oxide layer.
6. The device as claimed in claim 1 , wherein the gate electrode includes a conductive layer.
7. The device as claimed in claim 6 , wherein the conductive layer has a side surface that is laterally spaced apart from sidewalls of the insulating patterns.
8. The device as claimed in claim 6 , wherein the conductive layer includes a barrier layer and a layer that is made of metal silicide or tungsten and is in contact with the barrier layer.
9. The device as claimed in claim 8 , wherein the diffusion barrier structure has a portion that is farther from the sidewalls of the insulating patterns than a side surface of the barrier layer adjacent to the sidewalls of the insulating patterns.
10. The device as claimed in claim 1 , wherein the diffusion barrier structure is self-aligned with the gate electrode.
11. A semiconductor device, comprising:
vertical stacks of alternating insulating patterns and electrodes on a substrate;
pillars connected to the substrate through the stacks;
a trench interposed horizontally between the stacks;
an insulator in the trench covering a sidewall of each of the stacks; and
a spacer between each electrode and the insulator, wherein the spacer includes an air gap between at least one of the electrodes and the insulator.