Semiconductor device and designing method of semiconductor device
Out of a plurality of transistors, in a power switch which controls, for each logic block, a supply and an interruption of power with respect to the each logic block, each having a gate electrode connected to a well via a contact electrode, and a body region connected to a connection portion of the well with the contact electrode via a well resistor under an element isolation insulating film, and controlling a threshold voltage by changing an electric potential applied to the body region in accordance with a signal of the gate electrode, a plurality of first transistors and a plurality of second transistors which are different from the plurality of first transistors are made to have different delay characteristics from each other between the respective connection portions of the well with the contact electrodes and the respective body regions.
1. A semiconductor device, comprising:
a plurality of logic blocks in which a power supply thereto is controlled; and
a plurality of power switches each of which controls, for each logic block of the plurality of logic blocks, a supply and an interruption of power with respect to the each logic block, wherein
each power switch of the plurality of power switches includes a plurality of transistors arranged in parallel between the each logic block and a power supply line of the power supply, each transistor of the plurality of transistors including a gate electrode connected to a well via a contact electrode, and a body region connected to a connection portion of the well with the contact electrode via a well resistor under an element isolation insulating film, having a delay characteristic which is a time constant based on a resistance value of the well resistor between the connection portion of the well with the contact electrode and the body region, and controlling a threshold voltage by changing an electric potential applied to the body region in accordance with a signal of the gate electrode, wherein
the plurality of transistors include a plurality of first transistors having a first delay characteristic and a plurality of second transistors different from the plurality of first transistors having a second delay characteristic different from the first delay characteristic.
2. The semiconductor device according to claim 1 , wherein
a resistance value of well resistors of the plurality of first transistors is different from a resistance value of well resistors of the plurality of second transistors.
3. The semiconductor device according to claim 1 , wherein
the semiconductor is provided a plurality of first regions being disposed the contact electrodes each connecting the gate electrode of the each transistor and the well, wherein
the delay characteristics are adjusted by thinning out the contact electrodes disposed on the plurality of first regions.
4. The semiconductor device according to claim 1 , wherein
the gate electrodes of adjacent transistors of the plurality of transistors are separated, and the separated gate electrodes are connected via well resistors under element isolation insulating films.
5. The semiconductor device according to claim 1 , wherein:
the plurality of transistors provided in the each power switch are formed in a second well of a second conductivity type located on a first well of a first conductivity type; and
the semiconductor device further comprises a control circuit which controls a voltage applied to the first well.