IP Library Granted Patent US 9,713,922
Granted Patent B2
US 9,713,922 · App. 15/370,408 · Granted Jul 25, 2017

Liquid discharging apparatus, head unit, capacitive load driving circuit, and integrated circuit device for capacitive load driving

Inventor: Takafumi Sano (Matsumoto, JP)
Assignee: Seiko Epson Corporation
B41J2/04541B41J2/14233B41J2002/14491
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Quick Facts
Patent No.
US 9,713,922
App. No.
15/370,408
Granted
Jul 25, 2017
Kind
B2
Abstract

There is provided a driving circuit for a capacitive load including: a modulation portion which generates a modulation signal pulse-modulated from a source signal; a gate driver which generates an amplification control signal based on the modulation signal; a boosting circuit which boosts and supplies a voltage to the gate driver; a transistor which generates an amplification modulation signal amplified from the modulation signal based on the amplification control signal; a low pass filter which demodulates the amplification modulation signal and generates a driving signal; and in which a wiring impedance between the ground terminal and the gate driver is smaller than a wiring impedance between the ground terminal and the boosting circuit.

Claims (22)

1. A driving circuit for driving a capacitive load, comprising:

a modulator which generates a modulation signal pulse-modulated from a source signal;

a gate driver which generates an amplification control signal based on the modulation signal;

a boosting circuit which boosts and supplies a voltage to the gate driver;

a transistor which generates an amplification modulation signal amplified from the modulation signal based on the amplification control signal; and

a low pass filter which demodulates the amplification modulation signal, generates a driving signal, and outputs the driving signal to the capacitive load,

wherein the gate driver and the boosting circuit are electrically connected to a common ground terminal, and

wherein a wiring impedance between the ground terminal and the gate driver is smaller than a wiring impedance between the ground terminal and the boosting circuit.

2. The driving circuit for driving a capacitive load, according to claim 1 ,

wherein the gate driver is configured of a first gate driver and a second gate driver which is operated on a lower potential side than the first gate driver,

wherein the second gate driver and the boosting circuit are electrically connected to the common ground terminal, and

wherein a wiring impedance between the ground terminal and the second gate driver is smaller than a wiring impedance between the ground terminal and the boosting circuit.

3. The driving circuit for driving a capacitive load, according to claim 1 ,

wherein the boosting circuit is a charge pump circuit.

4. The driving circuit for driving a capacitive load, according to claim 1 ,

wherein the oscillation frequency of the modulation signal is 1 MHz to 8 MHz.

5. An integrated circuit for driving a capacitive load, comprising:

a modulator which generates a modulation signal pulse-modulated from a source signal;

a gate driver which generates an amplification control signal based on the modulation signal, and outputs the amplification control signal to an output circuit that generates a driving signal based on the amplification control signal and outputs the driving signal to the capacitive load; and

a boosting circuit which boosts and supplies a voltage to the gate driver,

wherein the gate driver and the boosting circuit are electrically connected to a common ground terminal, and

wherein a wiring impedance between the ground terminal and the gate driver is smaller than a wiring impedance between the ground terminal and the boosting circuit.

Priority Claims (1)
JP 2014-253381 · Dec 15, 2014 · national
Continuity (2)
Division 14950495 · Nov 24, 2015
Related Publication 20170080708A1 · Mar 23, 2017