Semiconductor structure including patterned feature
A multiple patterning method is provided. The multiple patterning method includes providing a substrate; and forming a sacrificial film on the substrate. The multiple patterning method also includes forming a first mask film on the sacrificial film; and forming a second mask film for subsequently forming a certain structure to protect the subsequently formed mask structures on the first mask film. Further, the multiple patterning method includes forming first mask structures and second mask structures by etching the second mask film, the first mask film, and the sacrificial film.
1. A semiconductor structure having a plurality of patterned features, comprising:
a substrate having a first region and a second region;
a plurality of first patterned features with a first critical dimension formed on the substrate in the first region; and
a plurality of second patterned features with a second critical dimension formed on the substrate in the second region, wherein:
the first critical dimension is smaller than the second critical dimension; and
the first patterned features and the second patterned features are formed by:
forming a sacrificial film on a surface of the substrate;
forming a first mask film on a surface of the sacrificial film; and
forming a second mask film on a surface of the first mask film.
2. The semiconductor structure according to claim 1 , after forming the second mask film further including:
forming a plurality of first mask structures having a first sacrificial layer, a first mask layer, and a second mask layer in the first region, and a plurality of second mask structures having a second sacrificial layer, a third mask layer; and a fourth mask layer for protecting the third mask layer in the second region by etching the second mask film, the first mask film, and the sacrificial film until the surface of the substrate is exposed;
etching the first mask layer and the third mask layer until the first mask layer is removed and the third mask layer has a certain lateral recess;
forming a first sidewall mask on side surfaces of the first sacrificial layer, and a second sidewall mask on side surfaces of the second sacrificial layer, the third mask layer, and the fourth mask layer;
removing the fourth mask layer;
removing the first sacrificial layer; and
etching the substrate using the first sidewall mask, and the second sidewall mask, and the third mask layer as an etching mask.
3. The semiconductor structure according to claim 2 , wherein:
the second mask layer and the fourth mask layer are removed simultaneously.
4. The semiconductor structure according to claim 2 , wherein:
the first mask layer and the second mask layer are removed simultaneously.
5. The semiconductor structure to claim 1 , wherein:
the substrate includes a semiconductor substrate, a to-be-etched layer, a device layer, electrical interconnect structures, and a dielectric layer.
6. The semiconductor structure according to claim 1 , wherein:
the sacrificial film is made of one of bottom anti-reflective material, amorphous carbon, and silicon;
the first mask film is made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon germanium, and silicon; and
the second mask film is made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon germanium, and silicon.
7. The semiconductor structure according to claim 1 , wherein:
the second critical dimension is approximately equal to or greater than three times of the first critical dimension.
8. The semiconductor structure according to claim 1 , wherein:
an etching selectivity ratio of the first mask film to the second mask film, the substrate, the first sidewall mask or the second sidewall mask may be greater than approximately two.
9. The semiconductor structure according to claim 1 , wherein:
the second mask film is made of a material different from the first sidewall mask or the second sidewall mask.