Stacked semicondcutor structure and method
A device comprises a first chip comprising a plurality of first interconnect structures over a first substrate, a plurality of first connection pads over the plurality of first interconnect structures and a plurality of first bonding pads, wherein a first bonding pad is formed over a corresponding first connection pad, and a second chip comprising a plurality of second interconnect structures over a second substrate and a plurality of second bonding pads over the plurality of second interconnect structures, wherein the first chip and the second chip are face-to-face bonded together, and wherein a first bonding pad is in direct contact with a corresponding second bonding pad.
1. An apparatus comprising:
a first chip comprising:
a plurality of first active circuits formed in a first substrate;
a first dielectric layer formed over the first substrate;
a plurality of first connection pads embedded in the first dielectric layer; and
a plurality of first bonding pads embedded in the first dielectric layer, wherein a first bonding pad is formed over a corresponding connection pad; and
a second chip comprising:
a plurality of second active circuits formed in a second substrate;
a second dielectric layer formed over the second substrate; and
a plurality of second bonding pads embedded in the second dielectric layer, wherein the first chip and the second chip are face-to-face bonded together, and wherein a first bonding pad is electrically coupled to a corresponding second bonding pad.
2. The apparatus of claim 1 , further comprising:
a first interconnect structure formed between the first substrate and the first dielectric layer; and
a second interconnect structure formed between the second substrate and the second dielectric layer.
3. The apparatus of claim 2 , wherein:
the first connection pads are electrically coupled to the first active circuits through the first interconnect structure.
4. The apparatus of claim 2 , wherein:
the second bonding pads are electrically coupled to the second active circuits through the second interconnect structure.
5. The apparatus of claim 2 , further comprising:
a plurality of second connection pads formed over a backside of the second interconnect structure.
6. The apparatus of claim 1 , further comprising:
a tungsten connector formed between the first bonding pad and the corresponding connection pad.
7. The apparatus of claim 1 , wherein:
the first bonding pads are formed of copper; and
the second bonding pads are formed of copper.
8. A device comprising:
a first chip comprising:
a plurality of first interconnect structures over a first substrate;
a plurality of first connection pads over the plurality of first interconnect structures; and
a plurality of first bonding pads, wherein a first bonding pad is formed over a corresponding first connection pad; and
a second chip comprising:
a plurality of second interconnect structures over a second substrate; and
a plurality of second bonding pads over the plurality of second interconnect structures, wherein the first chip and the second chip are face-to-face bonded together, and wherein a first bonding pad is in direct contact with a corresponding second bonding pad, wherein a width of a second bonding pad is greater than a width of a first bonding pad in direct contact with the second bonding pad.
9. The device of claim 8 , wherein:
the first bonding pad is in direct contact with the corresponding first connection pad.
10. The device of claim 8 , wherein:
the plurality of first connection pads are formed of aluminum; and
the plurality of first bonding pads are formed of copper.
11. The device of claim 8 , further comprising:
a first dielectric layer over the first chip, wherein the plurality of first connection pads and the plurality of first bonding pads are embedded in the first dielectric layer; and
a second dielectric layer over the second chip, wherein the plurality of second bonding pads are embedded in the second dielectric layer.
12. The device of claim 8 , further comprising:
a second connection pad on a non-bonding side of the second chip, wherein:
a first surface of the second connection pad is level with a first surface of the second substrate; and
a second surface of the second connection pad is lower than a second surface of the second substrate.
13. The device of claim 8 , wherein:
at least one second bonding pad of the plurality of second bonding pads is in direct contact with a surface of a metal line of the second chip.
14. The device of claim 8 , further comprising:
a connector between a first connection pad and a first bonding pad.
15. The device of claim 14 , wherein:
the connector is formed of tungsten.
16. A structure comprising:
a first chip comprising:
a first connection pad over a first substrate; and
a first bonding pad and a second bonding pad on the first connection pad; and
a second chip comprising:
a metal line over a second substrate; and
a third bonding pad and a fourth bonding pad on the metal line, wherein a distance between the first bonding pad and the second bonding pad is greater than a distance between the third bonding pad and the fourth bonding pad, and wherein:
the first bonding pad is in direct contact with the third bonding pad; and
the second bonding pad is in direct contact with the fourth bonding pad.
17. The structure of claim 16 , wherein:
a width of the third bonding pad is greater than a width of the first bonding pad; and
a width of the fourth bonding pad is greater than a width of the second bonding pad.
18. The structure of claim 16 , wherein:
the first chip is face-to-face bonded on the second chip.
19. The structure of claim 16 , further comprising:
a second connection pad and a third connection pad on a non-bonding side of the second chip, wherein:
the second substrate is between the second connection pad and the third connection pad.
20. The structure of claim 19 , wherein:
a non-bonding surface of the second substrate is higher than a non-bonding surface of the second connection pad.