Semiconductor device with surrounding gate transistors in a NAND circuit
A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NAND circuit. The NAND circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NAND circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NAND circuit.
1. A semiconductor device, comprising:
a plurality of transistors arranged in two rows and n columns on a substrate, where n≧4, to constitute a NAND circuit having g input signals, where n=h×g, and each of g and h is an integer, each of the plurality of transistors having a source, a drain, and a gate arranged in layers in a direction perpendicular to the substrate,
each of the plurality of transistors including:
a silicon pillar,
an insulator surrounding a side surface of the silicon pillar,
a gate surrounding the insulator,
a source region disposed on an upper portion or a lower portion of the silicon pillar, and
a drain region disposed on an upper portion or a lower portion of the silicon pillar, the drain region being located on a side of the silicon pillar opposite to a side of the silicon pillar on which the source region is located,
the plurality of transistors including:
n p-channel MOS transistors arranged in one row and n columns, and
n n-channel MOS transistors arranged in one row and n columns,
wherein the n p-channel MOS transistors and the n n-channel MOS transistors are arranged such that
a p-channel MOS transistor in a k-th column and an n-channel MOS transistor in the k-th column form a pair, where k=1 to n, the gate of the p-channel MOS transistor in the k-th column and the gate of the n-channel MOS transistor in the k-th column being connected to one another,
the drain regions of the n p-channel MOS transistors and the drain regions of h n-channel MOS transistors in first to h-th columns are located on a side of the silicon pillars close to the substrate, and are connected to one another via a silicide region, and
the n columns are grouped into g sets each having h columns, and the source regions of n-channel MOS transistors in a g-th set and the drain regions of n-channel MOS transistors in a (g+1)-th set are connected to one another.
2. The semiconductor device according to claim 1 , wherein:
the source regions of the n p-channel MOS transistors are connected to a power supply line extending along a row, and
the source regions of h n-channel MOS transistors in a last set among the g sets are connected to a reference power supply line extending along a row.
3. The semiconductor device according to claim 1 , wherein h n-channel MOS transistors grouped in the g-th set are arranged such that the source regions of n-channel MOS transistors in an even-numbered set are located on the side of the silicon pillars close to the substrate.
4. The semiconductor device according to claim 1 , wherein each of the g input signals is connected to gates of arbitrary h pairs of transistors among n sets of pairs of transistors whose gates are connected to one another.
5. The semiconductor device according to claim 2 , wherein each of the power supply line and the reference power supply line comprises a first metal line, and each of the g input signals comprises a second metal line extending in a direction perpendicular to the power supply line and the reference power supply line.