Vertical field-effect-transistors having multiple threshold voltages
Various embodiments disclose a method for fabricating a semiconductor structure including a plurality of vertical transistors each having different threshold voltages. In one embodiment the method includes forming a structure having at least a substrate, a source contact layer on the substrate, a first spacer layer on the source contact layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer. A first trench is formed in a first region of the structure. A first channel layer having a first doping concentration is epitaxially grown in the first trench. A second trench is formed in a second region of the structure. A second channel layer having a second doping concentration is epitaxially grown in the second trench. The second doping concentration is different from the first doping concentration.
1. A semiconductor structure comprising:
a first vertical field-effect transistor comprising a first threshold voltage; and
at least a second vertical field-effect transistor comprising a second threshold voltage that is different from the first threshold voltage,
wherein each of the first and second vertical field-effect transistors comprises at least:
a substrate;
a source contact layer on the substrate;
a first spacer layer on the source contact layer;
a second spacer layer;
a metal gate in contact with sidewalls of an epitaxially grown channel layer, a top surface of the first spacer layer, and a bottom surface of the second spacer layer.
2. The semiconductor structure of claim 1 , wherein the epitaxially grown channel layer of the first vertical field-effect transistor comprises a first doping concentration, and wherein the epitaxially grown channel layer of the second vertical field-effect transistor comprises a second doping concentration that is different from the first doping concentration.
3. The semiconductor structure of claim 1 , wherein the epitaxially grown channel layer of each of the first and second vertical field-effect transistors comprises a narrowed portion above a bottom surface of the second spacer layer that extends above a top surface of the second spacer layer.
4. The semiconductor structure of claim 3 , wherein each of the first and second vertical field-effect transistors comprises:
a drain region formed on and in contact with sidewalls of the narrowed portion of the epitaxially grown channel layer and a top surface of a portion of the epitaxially grown channel layer that is below the narrowed portion of the epitaxially grown channel layer.
5. An integrated circuit comprising:
a semiconductor structure, the semiconductor structure comprising
a first vertical field-effect transistor comprising a first threshold voltage; and
at least a second vertical field-effect transistor comprising a second threshold voltage that is different from the first threshold voltage,
wherein each of the first and second vertical field-effect transistors comprises at least:
a substrate;
a source contact layer on the substrate;
a first spacer layer on the source contact layer;
a second spacer layer;
a metal gate in contact with sidewalls of an epitaxially grown channel layer, a top surface of the first spacer layer, and a bottom surface of the second spacer layer.
6. The integrated circuit of claim 5 , wherein the epitaxially grown channel layer of the first vertical field-effect transistor comprises a first doping concentration, and wherein the epitaxially grown channel layer of the second vertical field-effect transistor comprises second doping concentration that is different than the first doping concentration.
7. The semiconductor structure of claim 1 , wherein each of the first and second vertical field-effect transistors further comprises a counter-doped layer in contact with the substrate.
8. The semiconductor structure of claim 1 , wherein each of the first and second vertical field-effect transistors further comprises a dielectric layer in contact with at least the first spacer, the epitaxially grown channel layer, and the second spacer.
9. The semiconductor structure of claim 8 , wherein each of the first and second vertical field-effect transistors further comprises a metal gate in contact with the dielectric layer.
10. The semiconductor structure of claim 4 , wherein a portion of the drain region layer extends below a top surface of the second spacer layer.
11. The semiconductor structure of claim 4 , wherein each of the first and second vertical field-effect transistors further comprises a dielectric material in contact with at least the drain region.
12. The semiconductor structure of claim 4 , wherein a portion of the drain region extends over the second spacer.
13. The integrated circuit of claim 5 , wherein the epitaxially grown channel layer of each of the first and second vertical field-effect transistors comprises a narrowed portion above a bottom surface of the second spacer layer that extends above a top surface of the second spacer layer.
14. The integrated circuit of claim 5 , wherein each of the first and second vertical field-effect transistors comprises:
a drain region formed on and in contact with sidewalls of the narrowed portion of the epitaxially grown channel layer and a top surface of a portion of the epitaxially grown channel layer that is below the narrowed portion of the epitaxially grown channel layer.
15. The integrated circuit of claim 14 , wherein a portion of the drain region layer extends below a top surface of the second spacer layer.
16. The integrated circuit of claim 14 , wherein each of the first and second vertical field-effect transistors further comprises a dielectric material in contact with at least the drain region.
17. The integrated circuit of claim 16 , wherein each of the first and second vertical field-effect transistors further comprises a metal gate in contact with the dielectric layer.
18. The integrated circuit of claim 14 , wherein a portion of the drain region extends over the second spacer.
19. The integrated circuit of claim 5 , wherein each of the first and second vertical field-effect transistors further comprises a counter-doped layer in contact with the substrate.
20. The integrated circuit of claim 5 , wherein each of the first and second vertical field-effect transistors further comprises a dielectric layer in contact with at least the first spacer, the epitaxially grown channel layer, and the second spacer.