Technique for performing memory access operations via texture hardware

1. A computer-implemented method for performing a data access operation, the method comprising:

receiving a first memory access request;

determining that the first memory access request represents a generic data access operation;

configuring a texture processing pipeline to perform generic data access operations instead of texture data access operations by configuring a texture-oriented processing engine within the texture processing pipeline to pass the first memory access request to a subsequent processing engine within the texture processing pipeline without a level-of-detail operation or an address computation operation being performed by; and

performing the generic data access operation by retrieving a portion of generic data from a location that is derived from the first memory access request.

2. The computer-implemented method of claim 1 , wherein determining that the first memory access request represents the generic data access operation comprises:

extracting a state index from the first memory access request; and

determining that a portion of the state index matches a value stored by a request register.

3. The computer-implemented method of claim 2 , wherein the value of the request register is configured by a software application executing on the processing unit.

4. The computer-implemented method of claim 1 , wherein performing the generic data access operation comprises:

determining that a virtual address included within the first memory access request is present within an entry included within a tag table;

retrieving an offset from a tag table based on the virtual address; and

retrieving the portion of generic data from a cache memory unit based on the offset.

5. The computer-implemented method of claim 1 , wherein performing the generic data access operation comprises:

determining that a virtual address included within the first memory access request is not present within an entry included within a tag table;

causing a miss processing unit to retrieve the portion of generic data from a physical location associated with a physical address derived from the virtual address.

6. The computer-implemented method of claim 1 , further comprising:

receiving a second memory access request;

determining that the second memory access request represents a texture data access operation;

configuring the texture processing pipeline to perform texture data access operations instead of generic data access operations; and

performing the texture data access operation by retrieving a portion of texture data from a location that is derived from the second memory access request.

7. The computer-implemented method of claim 1 , wherein configuring the texture processing pipeline to perform generic data access operations instead of texture data access operations further comprises configuring a tag unit to extract an offset associated with a cache unit from within a tag table based on a virtual address included within the first memory access request instead of a u-coordinate and v-coordinate included within the first memory access request.

8. A non-transitory computer-readable medium storing program instructions that, when executed by a processor, cause the processor to perform a data access operation by performing the steps of:

receiving a first memory access request;

determining that the first memory access request represents a generic data access operation;

configuring a texture processing pipeline to perform generic data access operations instead of texture data access operations by configuring a texture-oriented processing engine within the texture processing pipeline to pass the first memory access request to a subsequent processing engine within the texture processing pipeline without performing an operation that extracts a u-coordinate or a v-coordinate from the first memory access request; and

performing the generic data access operation by retrieving a portion of generic data from a location that is derived from the first memory access request.

9. The non-transitory computer-readable medium of claim 8 , wherein the step of determining that the first memory access request represents the generic data access operation comprises:

extracting a state index from the first memory access request; and

determining that a portion of the state index matches a value stored by a request register.

10. The non-transitory computer-readable medium of claim 9 , wherein the value of the request register is configured by a software application executing on the processing unit.

11. The non-transitory computer-readable medium of claim 8 , wherein the step of performing the generic data access operation comprises:

determining that a virtual address included within the first memory access request is present within an entry included within a tag table;

retrieving an offset from a tag table based on the virtual address; and

retrieving the portion of generic data from a cache memory unit based on the offset.

12. The non-transitory computer-readable medium of claim 8 , wherein the step of performing the generic data access operation comprises:

determining that a virtual address included within the first memory access request is not present within an entry included within a tag table;

causing a miss processing unit to retrieve the portion of generic data from a physical location associated with a physical address derived from the virtual address.

13. The non-transitory computer-readable medium of claim 8 , further comprising the steps of:

receiving a second memory access request;

determining that the second memory access request represents a texture data access operation;

configuring the texture processing pipeline to perform texture data access operations instead of generic data access operations; and

performing the texture data access operation by retrieving a portion of texture data from a location that is derived from the second memory access request.

14. The non-transitory computer-readable medium of claim 8 , wherein the step of configuring the texture processing pipeline to perform generic data access operations instead of texture data access operations further comprises configuring a tag unit to extract an offset associated with a cache unit from within a tag table based on a virtual address included within the first memory access request.

15. A computing device configured to perform a data access operation, including:

a memory that stores instructions; and

a processor coupled to the memory and, when executing the instructions, is

configured to:

receive a first memory access request;

determine that the first memory access request represents a generic data access operation;

configure a texture processing pipeline to perform generic data access operations instead of texture data access operations by configuring a texture-oriented processing engine within the texture processing pipeline to pass the first memory access request to a subsequent processing engine within the texture processing pipeline without a level-of-detail operation or an address computation operation being performed; and

perform the generic data access operation by retrieving a portion of generic data from a location that is derived from the first memory access request.

16. The computing device of claim 15 , wherein the processor is configured to determine that the first memory access request represents the generic data access operation by:

extracting a state index from the first memory access request; and

determining that a portion of the state index matches a value stored by a request register, wherein the value of the request register is configured by a software application executing on the processing unit.

17. The computing device of claim 15 , wherein the processor is configured to perform the generic data access operation by:

determining that a virtual address included within the first memory access request is present within an entry included within a tag table;

retrieving an offset from a tag table based on the virtual address; and

retrieving the portion of generic data from a cache memory unit based on the offset.