IP Library › Granted Patent US 9,721,951
Granted Patent B2
US 9,721,951 · App. 14/577,209 · Granted Aug 1, 2017

Semiconductor device using Ge channel and manufacturing method thereof

Inventors: Keiji Ikeda (Tokyo, JP); Tsutomu Tezuka (Ibaraki, JP); Yuuichi Kamimuta (Mie, JP); Kiyoe Furuse (Chiba, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L27/092H01L21/02532H01L21/02592H01L21/02667H01L21/324H01L21/823807H01L23/5226H01L25/0657H01L27/0207H01L27/0688H01L29/165H01L29/4966H01L29/517H01L21/823871H01L21/823878H01L27/0922H01L27/1203H01L29/78684H01L2225/06513H01L2225/06541H01L2924/0002
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Quick Facts
Patent No.
US 9,721,951
App. No.
14/577,209
Granted
Aug 1, 2017
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes a first complementary semiconductor device provided on a semiconductor substrate, and including a CMOS circuit, a metal electrode provided above the first complementary semiconductor device, a semiconductor layer provided above the metal electrode, including an nMOS region and a pMOS region separated from each other, and containing Ge; and a second complementary semiconductor device including an nMOSFET provided on the first portion of the semiconductor layer and a pMOSFET provided on the second portion of the semiconductor layer.

Claims (17)

1. A semiconductor device comprising:

a first complementary semiconductor device provided on a semiconductor substrate, and including a CMOS circuit;

a metal electrode provided above the first complementary semiconductor device;

a semiconductor layer provided above the metal electrode, including an nMOS region and a pMOS region separated from each other, and containing Ge;

a second complementary semiconductor device including an nMOSFET provided on the nMOS region of the semiconductor layer and a pMOSFET provided on the pMOS region of the semiconductor layer;

a work function control layer provided between the metal electrode and the semiconductor layer including the nMOS region and the pMOS region; and

an insulating film provided between the semiconductor layer and the work function control layer.

2. The device of claim 1 , wherein the metal electrode comprises a first portion below the nMOS region and a second portion below the pMOS region and separated from the first portion.

3. The device of claim 2 , further comprising:

a first signal line connected to the first portion of the metal electrode; and

a second signal line connected to the second portion of the metal electrode independently.

4. The device of claim 2 , further comprising a common signal line connected to the first portion of the metal electrode and the second portion of the metal electrode.

5. The device of claim 1 , wherein the work function control layer comprises one of TiN and TaN, and the insulating film comprises a rare-earth oxide.

6. The device of claim 1 , wherein the work function control layer comprises one of TiN and TaN, and the insulating film comprises one of a hafnium oxide, an aluminum oxide and a hafnium aluminum oxide.

7. The device of claim 1 , wherein the metal electrode is included in an uppermost layer of wiring layers above the first complementary semiconductor device, and the second complementary semiconductor device is electrically connected to the first complementary semiconductor device.

8. The device of claim 1 , wherein the metal electrode is included in an intermediate layer of wiring layers above the first complementary semiconductor device, and the second complementary semiconductor device is electrically connected to the first complementary semiconductor device.

9. The device of claim 1 , wherein the first complementary semiconductor device is provided on a Si substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2015
From: IKEDA, KEIJI; TEZUKA, TSUTOMU; KAMIMUTA, YUUICHI; FURUSE, KIYOE
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 034962/0436 →
Priority Claims (1)
JP 2012-138103 · Jun 19, 2012 · national
Continuity (2)
Continuation PCTJP2013055527 · Feb 28, 2013
Related Publication 20150102419A1 · Apr 16, 2015