Semiconductor devices and methods of manufacturing the same
Provided are semiconductor devices and methods of manufacturing the same. A semiconductor device may include a source, a drain, a semiconductor element between the source and the drain, and a graphene layer that is provided on the source and the semiconductor element and is spaced apart from the drain. Surfaces of the source and the drain are substantially co-planar with a surface of the semiconductor element. The semiconductor element may be spaced apart from the source and may contact the drain. The graphene layer may have a planar structure. A gate insulating layer and a gate may be provided on the graphene layer. The semiconductor device may be a transistor. The semiconductor device may have a barristor structure. The semiconductor device may be a planar type graphene barristor.
1. A semiconductor device comprising:
a source and a drain that are spaced apart from each other;
a semiconductor element between the source and the drain, the semiconductor element being spaced apart from the source and contacting the drain;
a graphene layer on the source and the semiconductor element to connect the source and the semiconductor element, the graphene layer being spaced apart from the drain;
a gate insulating layer on the graphene layer; and
a gate on the gate insulating layer;
wherein a level difference between surfaces of the source and the drain and a surface of the semiconductor element is about 5 nm or less.
2. The semiconductor device of claim 1 , wherein surfaces of the source and the drain are substantially co-planar with a surface of the semiconductor element.
3. The semiconductor device of claim 1 , wherein an isolation layer is provided between the source and the semiconductor element, and a level difference between surfaces of the source and the drain and a surface of the isolation layer is about 5 nm or less.
4. The semiconductor device of claim 1 , wherein the graphene layer has a flat structure.
5. The semiconductor device of claim 1 , wherein the semiconductor element comprises one of an n-type semiconductor and a p-type semiconductor.
6. The semiconductor device of claim 1 , wherein the semiconductor element comprises at least one selected from the group consisting of silicon (Si), germanium (Ge), silicon germanium (SiGe), and strained Si.
7. A semiconductor device comprising:
a source and a drain that are spaced apart from each other;
a semiconductor element between the source and the drain, the semiconductor element being spaced apart from the source and contacting the drain;
a graphene layer on the source and the semiconductor element to connect the source and the semiconductor element, the graphene layer being spaced apart from the drain;
a gate insulating layer on the graphene layer;
a gate on the gate insulating layer;
a passivation layer covering at least a portion of the source, the drain, the gate insulating layer, and the gate; and
a source pad and a drain pad that are provided on the passivation layer and are electrically connected to the source and the drain, respectively.
8. The semiconductor device of claim 1 , wherein the source and the drain each comprise an impurity-doped region.
9. The semiconductor device of claim 1 , wherein at least one of the source and the drain comprises metal silicide.
10. The semiconductor device of claim 1 , wherein at least one of the source and the drain comprises a metal or a metal compound.
11. The semiconductor device of claim 1 , wherein at least one of the source and the drain is on at least one of a silicon substrate and a silicon-on-insulator (SOI) substrate.
12. The semiconductor device of claim 1 , wherein the semiconductor device comprises a barristor device structure.
13. A method of manufacturing a semiconductor device, the method comprising:
preparing a device region comprising a source, a drain, and a semiconductor element between the source and the drain, the semiconductor element being spaced apart from the source and contacting the drain, wherein a level difference between surfaces of the source and the drain and a surface of the semiconductor element is about 5 nm or less;
forming a graphene layer on the source and the semiconductor element, the graphene layer being spaced apart from the drain;
forming a gate insulating layer on the graphene layer; and
forming a gate on the gate insulating layer above the semiconductor element.
14. The method of claim 13 , wherein the preparing of the device region comprises:
forming an isolation layer in a substrate, wherein the isolation layer defines regions for the source, the drain, and the semiconductor element; and
performing a planarization process with respect to surfaces of the source, the drain, the semiconductor element and the isolation layer, wherein
surfaces of the source and the drain are substantially co-planar with a surface of the semiconductor element.
15. The method of claim 14 , wherein the planarization process comprises a chemical mechanical polishing (CMP) process, wherein an etch stop layer is selectively used in the CMP process.
16. The method of claim 13 , wherein the device region is on a silicon substrate or a silicon-on-insulator (SOI) substrate.
17. The method of claim 13 , wherein each of the source and the drain comprise an impurity-doped region.
18. The method of claim 13 , wherein at least one of the source and the drain comprises metal silicide.
19. The method of claim 13 , wherein at least one of the source and the drain comprises a metal or a metal compound.