Semiconductor device and method for manufacturing the same
A transistor including an oxide semiconductor, which has good on-state characteristics, and a high-performance semiconductor device including a transistor capable of high-speed response and high-speed operation. In the transistor including an oxide semiconductor, oxygen-defect-inducing factors are introduced (added) into an oxide semiconductor layer, whereby the resistance of a source and drain regions are selectively reduced. Oxygen-defect-inducing factors are introduced into the oxide semiconductor layer, whereby oxygen defects serving as donors can be effectively formed in the oxide semiconductor layer. The introduced oxygen-defect-inducing factors are one or more selected from titanium, tungsten, and molybdenum, and are introduced by an ion implantation method.
1. A semiconductor device comprising:
an oxide semiconductor layer over an insulating surface;
a gate insulating layer over the oxide semiconductor layer;
a gate electrode layer over the gate insulating layer; and
a source electrode layer and a drain electrode layer over the oxide semiconductor layer,
wherein the oxide semiconductor layer comprises a channel formation region, a first region, and a second region,
wherein the first region is electrically connected to the source electrode layer,
wherein the second region is electrically connected to the drain electrode layer,
wherein each of the first region and the second region contains more of one or more elements selected from titanium, tungsten, molybdenum, cobalt, and silicon than the channel formation region, and
wherein the oxide semiconductor layer contains indium, gallium, and zinc.
2. The semiconductor device according to claim 1 , further comprising an insulating layer over the gate electrode layer.
3. A semiconductor device comprising:
an oxide semiconductor layer over an insulating surface;
a gate insulating layer over the oxide semiconductor layer;
a gate electrode layer over the gate insulating layer; and
a source electrode layer and a drain electrode layer over the oxide semiconductor layer,
wherein the oxide semiconductor layer comprises a channel formation region, a first region, and a second region,
wherein the first region is electrically connected to the source electrode layer,
wherein the second region is electrically connected to the drain electrode layer,
wherein the oxide semiconductor layer contains indium, gallium, and zinc,
wherein each of the first region and the second region contains more of one or more elements selected from titanium, tungsten, molybdenum, cobalt, and silicon than the channel formation region, and
wherein the oxide semiconductor layer includes a region including a crystal whose c-axis is aligned in a direction within ±10° from a perpendicular direction to a surface of the oxide semiconductor layer.
4. The semiconductor device according to claim 3 , further comprising a first insulating layer over the gate electrode layer.
5. The semiconductor device according to claim 4 , further comprising a second insulating layer over the first insulating layer.
6. A semiconductor device comprising:
an oxide semiconductor layer over an insulating surface;
a gate insulating layer over the oxide semiconductor layer;
a gate electrode layer over the gate insulating layer; and
a source electrode layer and a drain electrode layer over the oxide semiconductor layer,
wherein the oxide semiconductor layer comprises a channel formation region, a first region, and a second region,
wherein the first region is electrically connected to the source electrode layer,
wherein the second region is electrically connected to the drain electrode layer,
wherein the oxide semiconductor layer contains indium, gallium, and zinc,
wherein each of the first region and the second region contains more of one or more elements selected from titanium, tungsten, molybdenum, cobalt, and silicon than the channel formation region,
wherein the oxide semiconductor layer includes a region including a crystal whose c-axis is aligned in a direction within ±10° from a perpendicular direction to a surface of the oxide semiconductor layer, and
wherein a carrier concentration of the channel formation region is lower than 1×10 17 /cm 3 .
7. The semiconductor device according to claim 6 , further comprising a first insulating layer over the gate electrode layer.
8. The semiconductor device according to claim 7 , further comprising a second insulating layer over the first insulating layer.