Managing over-initiative thin interrupts

1. A method for identifying extraneous input/output interrupts for a queued input/output device architecture, the method comprising:

determining, with a processor, that at least one interrupt has been generated for at least one queue in a plurality of queues of a queued input/output device architecture;

determining a queue state associated with the queue; and

identifying that the at least one interrupt is one of an extraneous interrupt and a valid interrupt based on the queue state associated with the queue, wherein identifying that the at least one interrupt is a valid interrupt is in response to the queue state indicating one of

the queue fails to be associated with at least one reply message waiting to be dequeued for a previously processed interrupt, and

the queue comprises at least one pending reply message for a previously non-processed interrupt,

wherein the valid interrupt is processed by an interrupt handler.

2. The method of claim 1 , wherein identifying that the at least one interrupt is an extraneous interrupt comprises at least one of:

determining that the queue state indicates one of that the queue is associated with at least one reply message waiting to be dequeued for a previously processed interrupt; and

determining that the queue state indicates that the queue fails to comprise at least one pending reply message for a previously received non-processed interrupt.

3. The method of claim 1 , further comprising:

setting a global lock for the at least one interrupt, wherein the global lock prevents interrupt handlers other than an interrupt handler associated with the at least one interrupt from processing the interrupt.

4. The method of claim 1 , further comprising:

updating an extraneous interrupt counter in response to identifying the at least one interrupt as being an extraneous interrupt.

5. The method of claim 4 , further comprising:

identifying a number of extraneous interrupts that have been received based on the extraneous interrupt counter; and

displaying the number of extraneous interrupts that have been received to an user.

6. The method of claim 1 , further comprising:

updating a valid interrupt counter in response to identifying the at least one interrupt as being a valid interrupt.

7. An information processing system for identifying extraneous input/output interrupts for a queued input/output device architecture, the information processing system comprising:

a memory;

a processor communicatively coupled to the memory; and

an interrupt handler communicatively coupled to the memory and the processor, wherein the interrupt handler is configured to perform a method comprising:

determining that at least one interrupt has been generated for at least one queue in a plurality of queues of a queued input/output device architecture;

determining a queue state associated with the queue; and

identifying that the at least one interrupt is one of an extraneous interrupt and a valid interrupt based on the queue state associated with the queue, wherein identifying that the at least one interrupt is a valid interrupt is in response to the queue state indicating one of

the queue fails to be associated with at least one reply message waiting to be dequeued for a previously processed interrupt, and

the queue comprises at least one pending reply message for a previously non-processed interrupt,

wherein the valid interrupt is processed by an interrupt handler.

8. The information processing system of claim 7 , wherein the identifying that the at least one interrupt is an extraneous interrupt comprises at least one of:

determining that the queue state indicates one of that the queue is associated with at least one reply message waiting to be dequeued for a previously processed interrupt; and

determining that the queue state indicates that the queue fails to comprise at least one pending reply message for a previously received non-processed interrupt.

9. The information processing system of claim 7 , wherein the method further comprises:

setting a global lock for the at least one interrupt, wherein the global lock prevents other interrupt handlers from processing the interrupt.

10. The information processing system of claim 7 , wherein the method further comprises: updating an extraneous interrupt counter in response to identifying the at least one interrupt as being an extraneous interrupt.

11. The information processing system of claim 7 , wherein the method further comprises:

updating a valid interrupt counter in response to identifying the at least one interrupt as being a valid interrupt.

12. A computer program product for managing instructions within a processor, the computer program product comprising:

a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:

determining, with a processor, that at least one interrupt has been generated for at least one queue in a plurality of queues of a queued input/output device architecture;

determining a queue state associated with the queue; and

identifying that the at least one interrupt is one of an extraneous interrupt and a valid interrupt based on the queue state associated with the queue, wherein identifying that the at least one interrupt is a valid interrupt is in response to the queue state indicating one of

the queue fails to be associated with at least one reply message waiting to be dequeued for a previously processed interrupt, and

the queue comprises at least one pending reply message for a previously non-processed interrupt,

wherein the valid interrupt is processed by an interrupt handler.

13. The computer program product of claim 12 , wherein the identifying that the at least one interrupt is an extraneous interrupt comprises at least one of:

determining that the queue state indicates one of that the queue is associated with at least one reply message waiting to be dequeued for a previously processed interrupt; and

determining that the queue state indicates that the queue fails to comprise at least one pending reply message for a previously received non-processed interrupt.

14. The computer program product of claim 12 , wherein the method further comprises:

setting a global lock for the at least one interrupt, wherein the global lock prevents interrupt handlers other than an interrupt handler associated with the at least one interrupt from processing the interrupt.

15. The computer program product of claim 12 , wherein the method further comprises:

updating an extraneous interrupt counter in response to identifying the at least one interrupt as being an extraneous interrupt.

16. The computer program product of claim 15 , wherein the method further comprises:

identifying a number of extraneous interrupts that have been received based on the extraneous interrupt counter; and

displaying the number of extraneous interrupts that have been received to an user.

17. The computer program product of claim 12 , wherein the method further comprises:

updating a valid interrupt counter in response to identifying the at least one interrupt as being a valid interrupt.