Non-planar transistors and methods of fabrication thereof
Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region.
1. A non-planar transistor comprising:
a fin comprising a top surface and sidewalls, the fin comprising a first portion, a second portion, and a third portion disposed between the first and the second portion, the first portion comprising a first source/drain region, the second portion comprising a second source/drain region, the third portion comprising a channel region;
an epitaxial semiconductor layer on the top surface and sidewalls of the fin on opposing sides of the third portion, the epitaxial semiconductor layer having a first doping profile;
a dopant rich semiconductor layer having a second doping profile disposed over the epitaxial semiconductor layer, the dopant rich semiconductor layer comprising a first conductivity type, the first doping profile different than the second doping profile, the dopant rich semiconductor layer disposed over the first portion and the second portion;
the channel region comprising a second conductivity type opposite the first conductivity type; and
a silicide layer disposed on a top surface and sidewalls of the dopant rich semiconductor layer, wherein the silicide layer is adjacent to the dopant rich semiconductor layer.
2. The non-planar transistor of claim 1 , wherein the channel region physically contacts the dopant rich semiconductor layer.
3. The non-planar transistor of claim 2 , wherein the silicide layer is in contact with a source/drain region of the non-planar transistor, wherein an interface between the silicide layer and the dopant rich semiconductor layer comprises a Schottky barrier, and wherein a concentration of a dopant in the dopant rich semiconductor layer at an interface between the silicide layer and the dopant rich semiconductor layer is higher than a concentration of the dopant in the silicide layer at the interface.
4. The non-planar transistor of claim 3 , wherein a concentration of a dopant in the dopant rich semiconductor layer at an interface between the silicide layer and the dopant rich semiconductor layer is greater than about 10 19 cm −3 , wherein a Schottky barrier height for a majority charge carrier of the non-planar transistor at the interface between the silicide layer and dopant rich semiconductor layer is less than about 0.2 eV, wherein a thickness of the dopant rich semiconductor layer is less than about 10 nm.
5. The non-planar transistor of claim 1 , further comprising a gate electrode disposed over the channel region and a portion of the dopant rich semiconductor layer.
6. The non-planar transistor of claim 1 , wherein the silicide layer comprises a metal selected from a group consisting of Ni, Al, La, Er, Y, Yb, Dy, Gd, Ce, Tb, Pr, Er, Co, Pt, Pd and combinations thereof.
7. The non-planar transistor of claim 1 , wherein the dopant rich semiconductor layer and silicide layer extend under the fin opposite the top surface of the fin.
8. A device comprising:
a channel region on a first portion of a semiconductor fin, the semiconductor fin comprising a top surface and sidewalls;
a gate electrode over the channel region of the semiconductor fin;
an epitaxial layer on the top surface and sidewalls of the semiconductor fin on opposing sides of the channel region, the epitaxial layer having a first doping profile and a first doping concentration;
a doped semiconductor layer of a first material disposed over the epitaxial layer and having a second doping profile and a second doping concentration, wherein at least one of:
the first doping profile is different than the second doping profile; or
the first doping concentration is different than the second doping concentration;
a silicide layer contacting the doped semiconductor layer, the silicide layer comprising a silicide metal and the first material; and
a dopant rich region disposed in the doped semiconductor layer and abutting the silicide layer, the dopant rich region disposed on first and second source/drain regions, the channel region interposed between the first and second source/drain regions.
9. The device of claim 8 , wherein the doped semiconductor layer has a doping profile outside of the dopant rich region that is different from the doping profile within the dopant rich region.
10. The device of claim 9 , wherein the dopant rich region has a dynamic doping profile.
11. The device of claim 8 , wherein at least a portion of the dopant rich region is disposed under the gate electrode.
12. The device of claim 8 , wherein an interface between the silicide layer and the dopant rich region forms a Schottky barrier.
13. The device of claim 8 , wherein the first and second source/drain regions are in the semiconductor fin.
14. The device of claim 8 , wherein the silicide layer comprises a metal selected from a group consisting of Ni, Al, La, Er, Y, Yb, Dy, Gd, Ce, Tb, Pr, Er, Co, Pd, Pt and combinations thereof, and wherein the device comprises a double gate, a triple gate, or a gate all around transistor.
15. A device comprising:
a channel region on a first portion of a semiconductor fin, the semiconductor fin comprising a top surface and sidewalls, the semiconductor fin having a second portion comprising a first source/drain region, the semiconductor fin having a third portion comprising a second source/drain region, the first portion interposed between the second portion and the third portion;
a gate electrode over the channel region of the semiconductor fin;
an epitaxial semiconductor layer on the top surface and the sidewalls of a portion of the semiconductor fin on opposing sides of the gate electrode, the epitaxial semiconductor layer having a first doping profile;
a second semiconductor layer having a second doping profile over the epitaxial semiconductor layer, the first doping profile different than the second doping profile;
a silicide layer over the second semiconductor layer; and
a dopant rich layer having a uniform thickness disposed in the second semiconductor layer, the dopant rich layer adjacent to the silicide layer, the dopant rich layer disposed on the second and the third portions.
16. The device of claim 15 , wherein an interface between the silicide layer and the dopant rich layer forms a Schottky barrier.
17. The device of claim 16 , wherein a concentration of a dopant in the dopant rich layer at an interface between the silicide layer and the dopant rich layer is greater than about 10 19 cm −3 , wherein a Schottky barrier height for a majority charge carrier of the device at the interface between the silicide layer and dopant rich layer is less than about 0.2 eV, wherein a thickness of the dopant rich layer is less than about 10 nm.
18. The device of claim 15 , wherein at least a portion of the dopant rich layer is disposed under the gate electrode.
19. The device of claim 15 , wherein the silicide layer comprises a metal selected from a group consisting of Ni, Al, La, Er, Y, Yb, Dy, Gd, Ce, Tb, Pr, Er, NiSi 2 Al x and combinations thereof, and wherein the device comprises an NMOS transistor.
20. The device of claim 15 , wherein the dopant rich layer has a dynamic doping profile.