Methods and apparatus to preserve data of a solid state drive during a power loss event

1. An apparatus comprising:

a first memory cell;

a primary data cache;

an alternate data cache;

a secondary data cache, the primary data cache, the alternate data cache, and the secondary data cache to store at least a portion of data while the data is written to the first memory cell; and

a non-volatile memory controller to, in response to an instruction to abort a write operation to the first memory cell:

set the alternate data cache equal to a logical AND of the secondary data cache and the primary data cache;

perform a first sense operation of the first memory cell at a first sensing threshold;

set the alternate data cache equal to a logical AND of the alternate data cache and a first result of the first sense operation;

set the primary data cache equal to a logical AND of the primary data cache and an inverse value of the alternate data cache;

set the alternate data cache equal to a logical AND of the secondary data cache and the primary data cache;

perform a second sense operation of the first memory cell at a second sensing threshold;

set the alternate data cache equal to a logical AND of the alternate data cache and an inverse value of a second result of the second sense operation;

set the secondary data cache equal to a logical AND of the secondary data cache and the primary data cache;

set the secondary data cache equal to a logical OR of the secondary data cache or the primary data cache;

perform a third sense operation of the first memory cell at a third sensing threshold; and

set the primary data cache equal to a logical AND of the primary data cache and a third result of the third sensing operation.

2. The apparatus as defined in claim 1 , wherein the non-volatile memory controller is further to, upon the setting of the primary data cache equal to the logical AND of the primary data cache and a third result of the third sensing operation:

write, to a second memory cell, the data stored in the primary data cache; and

write, to a third memory cell, the data stored in the secondary data cache.

3. The apparatus as defined in claim 2 , wherein the second memory cell is the first memory cell.

4. The apparatus as defined in claim 2 , wherein the second memory cell is separate from the first memory cell.

5. The apparatus as defined in claim 2 , wherein the third memory cell is separate from the first memory cell and the second memory cell.

6. The apparatus as defined in claim 2 , wherein the first memory cell is included in a first memory block, and the second memory cell and the third memory cell are included in a second memory block separate from the first memory block.

7. The apparatus as defined in claim 6 , wherein the second memory block is operated in a dedicated single level cell mode.

8. The apparatus as defined in claim 1 , further including:

an energy storage circuit;

a power loss event detector to detect a main power loss event; and

an abort instructor to, using energy stored in the energy storage circuit, provide the instruction to abort the ongoing write operation to the non-volatile memory controller in response to the detection of the main power loss event.

9. A method for recovering data to be written to an aborted memory cell, the method comprising:

setting an alternate data cache equal to a logical AND of a secondary data cache and a primary data cache, wherein the alternate data cache, the secondary data cache, and the primary data cache are to store at least a portion of data while the data is written to the aborted memory cell;

performing a first sense operation of the aborted memory cell at a first sensing threshold;

setting the alternate data cache equal to a logical AND of the alternate data cache and a first result of the first sense operation;

setting the primary data cache equal to a logical AND of the primary data cache and an inverse value of the alternate data cache;

setting the alternate data cache equal to a logical AND of the secondary data cache and the primary data cache;

performing a second sense operation of the aborted memory cell at a second sensing threshold;

setting the alternate data cache equal to a logical AND of the alternate data cache and an inverse value of a second result of the second sense operation;

setting the secondary data cache equal to a logical AND of the secondary data cache and the primary data cache;

setting the secondary data cache equal to a logical OR of the secondary data cache or the primary data cache;

performing a third sense operation of the aborted memory cell at a third sensing threshold; and

setting the primary data cache equal to a logical AND of the primary data cache and a third result of the third sensing operation.

10. The method as defined in claim 9 , further including, upon the setting of the primary data cache equal to the logical AND of the primary data cache and a third result of the third sensing operation:

writing, to a first memory cell, the data stored in the primary data cache; and

writing, to a second memory cell, the data stored in the secondary data cache.

11. The method as defined in claim 10 , wherein the first memory cell is the aborted memory cell.

12. The method as defined in claim 10 , wherein the first memory cell is separate from the aborted memory cell.

13. The method as defined in claim 10 , wherein the second memory cell is separate from the aborted memory cell and the first memory cell.

14. The method as defined in claim 10 , wherein the aborted memory cell is included in a first memory block, and the first memory cell and the second memory cell are included in a second memory block separate from the first memory block.

15. The method as defined in claim 14 , wherein the second memory block is operated in a dedicated single level cell mode.

16. At least one tangible machine readable storage medium comprising instructions that, when executed, cause one or more processors to at least:

set an alternate data cache equal to a logical AND of a secondary data cache and a primary data cache, wherein the alternate data cache, the secondary data cache, and the primary data cache are to store at least a portion of data while the data is written to a memory cell;

perform a first sense operation of the memory cell at a first sensing threshold;

set the alternate data cache equal to a logical AND of the alternate data cache and a first result of the first sense operation;

set the primary data cache equal to a logical AND of the primary data cache and an inverse value of the alternate data cache;

set the alternate data cache equal to a logical AND of the secondary data cache and the primary data cache;

perform a second sense operation of the memory cell at a second sensing threshold;

set the alternate data cache equal to a logical AND of the alternate data cache and an inverse value of a second result of the second sense operation;

set the secondary data cache equal to a logical AND of the secondary data cache and the primary data cache;

set the secondary data cache equal to a logical OR of the secondary data cache or the primary data cache;

perform a third sense operation of the memory cell at a third sensing threshold; and

set the primary data cache equal to a logical AND of the primary data cache and a third result of the third sensing operation.

17. The at least one tangible machine readable storage medium as defined in claim 16 , wherein the instructions, when executed, further cause the machine to, upon the setting of the primary data cache equal to a logical AND of the primary data cache and a third result of the third sensing operation:

write, to a first memory cell, the data stored in the primary data cache; and

write, to a second memory cell, the data stored in the secondary data cache.

18. The at least one tangible machine readable storage medium as defined in claim 17 , wherein the first memory cell is the aborted memory cell.

19. The at least one tangible machine readable storage medium as defined in claim 17 , wherein the first memory cell is separate from the aborted memory cell.

20. The at least one tangible machine readable storage medium as defined in claim 17 , wherein the aborted memory cell is included in a first memory block, and the first memory cell and the second memory cell are included in a second memory block separate from the first memory block.